1、Assigned readings,SIGNALSTORM NANOMETER DELAY CALCULATOR,CADENCE DATASHEET,Introduction:,The movement of VLSI chips to nanometer process geometries resulted:to the domination of interconnect delays in total delayincreased sensitivity to variations in power supply New Challenges for the delay calcula
2、tors :cant model the wires as single lumped effective capacitance cant use linear approximation techniques for IR Drop and ground bounceCAD tools need to develop new algorithms for nanometer delay modelingSignalstorm is a popular tool for performing timing characterizations for standard cell librari
3、es.,Why Do We Need New Solution for Delay Prediction,Multilevel design methodologies allow great variation in power supply voltage tools must model this variation in a nonlinear fashion Modeling input pin capacitance was inaccurate because it is based on fixed values rather than dynamic values Model
4、ing dynamic current and capacitance characteristics should take into account of nonlinear IR Drop and wire loading effects.,Inadequate delay calculations lead design failures, and lack of competitiveness in the market because we might lose the advantages of nanometer technology.,What Are Essential C
5、apabilities for NDC?,Estimating Ceff,Gate Delay = f( Tin, Cload ),Gate Delay = f( Tin, Cload, Rpi, C2 ) Requires 4-D table to achieve high accuracy,Single C value that can be replaced instead of RC-Pi load,What Are Essential Capabilities for NDC?,Timequantized Model of Ceff Traditional tool use sing
6、le values for Ceff which results in up to 20% inaccurate slew values SignalStorm apply dynamic relationship between voltage, current and load capacitance to calculate slew and delay. SignalStorm computes over several time steps during signal ramp to more closely track the actual effective capacitanc
7、e as it changes with signal voltage.,Gate Delay = f( Tin, Cload ),What Are Essential Capabilities for NDC?,Variable Source Current Modeling with ECMs,Nonlinear current source fittingInput slew & output load dependence Accurate calculations at multiple driver cells, clock meshes, long interconnects,
8、modeling RC drop effects Most efficient current modeling because it can represent complex topologies more accurately,What Are Essential Capabilities for NDC?,IR Drop and Ground Bounce Effects on Timing at 130 nm IR Drop Describes the voltage drops caused by current flowing from power source through
9、a resistive power network to the on-chip devices. Ground Bounce Describes voltage spikes caused by current flowing from on-chip devices through a resistive ground network to the ground pins IR Drop and Ground Bounce impact silicon performance Increased clock skew hold time violations Increased signa
10、l skew setup time violations,Change In Delay With IR is Nonlinear,SignalStorm NDC In The Design Flow,Synopsis Primetime (Brendan),Stand-alone full chip, gate-level static timing analyzer. It analyzes the timing of large, synchronous, digital ASICs. Pre-layout static timing analysis,Static Timing Ana
11、lysis,Setup and hold checks Recovery and removal checks Clock pulse width checks Clock gating checks,Design Analysis,Unclocked registers Unconstrained timing endpoints Master-slave clock separation Multiple clocked registers Level-sensitive clocking Combinational feedback loops Design rule checks (m
12、aximum capacitance, maximum transition time, and maximum fanout),Inputs - Outputs,Design file Synopsys database files (.db) Verilog netlist files Electronic Data Interchange Format (EDIF) netlist files VHDL netlist files Set up the operating conditions, wireload models, port load, drive, and transit
13、ion time. Define the clock period, waveform, uncertainty, and latency. Specify the input and output port delays. Set multicycle paths. Set false paths. Specify minimum and maximum delays, path segmentation, and disabled arcs.,% flip-flops with violations setup and hold violations timing paths rising
14、 edge input timing and falling edge input timing of all paths in the design critical path for each clock group timing report for each clock group electrical design rule violations,Benefits,Tight integration with other Synopsis tools Standalone (lower memory usage than Design Compiler, better perform
15、ance) Primetime SI cross talk aware analysis,Alternatives,Dataquest (2004): Synopsis holds 93% of STA market share ViewLogic Motive Bought by Synopsis Spice More for validation Cadence Pearl Mentor Graphics SST Velocity,Further Information,PrimeTime Tutorial: 1. Introduction to PrimeTime and the Tut
16、orial Primetime Tutorial Have I Really Met Timing? - Validating PrimeTime Timing Reports with SpiceTobias ThielProceedings of the Design, Automation and Test in Europe Conference and Exhibition Designers Forum (DATE04),Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correla
17、tions Aseem Agarwal, David Blaauw, *Vladimir Zolotov University of Michigan, Ann Arbor, MI *Motorola, Inc., Austin, TX,Inter-die & Intra die variablilty,Gate length variability Intra-die variations Random variations (no dependence on location) Spatially correlated variations,Process variation model,
18、Ignoring all spatial correlationsGate length variations small with 3 values of less that 15% of Lnom The change in gate delay is linear with the change in gate length.,Correlations,Reconvergence of circuit paths Arrival time of nodes B and C are both dependent on the arrival time at node A Can be ig
19、nored. Gives the upper bound. For proof see: A. Agarwal et al “Computation and Refinement of Statistical Bounds on Circuit Delay” DAC 2003 Spatial correlation Between gate delay and arrival times (complicates the propagation) Between gate delays (complicates the merging of arrival times) Ignoring do
20、es not give the upper bound. WHY? Spatial correlation makes the intra-die variability more similar to that of inter-die variability, which increases the delay of circuit paths.,Modeling spatial correlation,Divide the die into 2lx2l squaresrandom variable associated with each region (l,r),Modeling sp
21、atial correlation,one of random variables in the model : for random variable associated with the gate based on its position in the die. For all other,TA Method: Propagation,Arrival times propagated from input to output of gates. Add gate delay and input arrival time to get output arrival time.,TA Me
22、thod: Merging,a1, a2 arrival times both in the sum of components form. max(a1,a2) Expensive: requires enumeration of the random variables Li Inaccurate: result does not preserve the spatial information for further propagation. GOAL: generate an output arrival time that is efficient and whose CDF is
23、an upper bound on the exact arrival time.,TA Method: Merging,INCREMENTAL TIMING ANALYSIS Patent Number: 5,508,937 Abato et al. Date of Patent: Apr. 16, 1996,Presented by Cesare,INCREMENTAL TIMING ANALYSIS: STA vs. ITA,STA (static timing analysis) nave approach: For each node of the circuit, calculat
24、e its couple. Observation: what happens if some circuit parameter changes? STA: NO PROBLEM Re-calculate the entire list of nodes (very inefficient solution) Better Approach: Incremental timing analysis,INCREMENTAL TIMING ANALYSIS: Overview,Circuit as a set of sub-circuits Each sub circuit is delimit
25、ed by leftmost nodes, and rightmost nodes What happens if we increment by 1 the rise/fall time of gate G1 ? The Arrival time for node Y changes Re-calculate the STA?,2/4,2/4 3/4,2/4,2/4,A,C,B,Sub Circuit_i,Leftmost nodes: A,B,C,Rightmost nodes: X,Y,X,Y,W1,W2,W3,W4,Arrival Time,Required Time,G1,INCRE
26、MENTAL TIMING ANALYSIS Algorithm,Basic Idea: Subdivide the circuit in N sub-regions Define the frontier of change nodes (rightmost and leftmost nodes). Store the frontiers of change are stored into two separate lists (Arrival queue Required Queue). Order the lists according to the the sub-circuit le
27、vel number If a node changes its timing propriety, discard the delay table of the respective sub-region DO NOT compute the STA for the sub-region until explicitly requested.,INCREMENTAL TIMING ANALYSIS: Notes,The frontiers of change move as recalculation progresses. The algorithm works recursively. Ordered lists for a fixed level, we can avoid to consider nodes with higher level. It is not needed to calculate the sub circuit STA every time a node changes!,INCREMENTAL TIMING ANALYSIS,ANY Questions? E N D,
