1、 JEDEC STANDARD Interoperability and Compliance Technical Requirements for JEDEC Standard JESD96A Recommended Practice for use with IEEE 802.11n JESD96A-1 (Addendum 1 to JESD96A, February 2006) JANUARY 2007 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain mate
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10、a 22201-3834 or call (703) 907-7559 JEDEC Standard No. 96-1 -i- INTEROPERABILITY AND COMPIANCE FOR THE RADIO FRONT ENDBASEBAND (RF-BB) INTERFACE STANDARD (JESD96) CONTENTS Foreward. ii Introduction ii 1 Scope 1 2 References2 2.1 Informative .2 2.2 Normative .2 3 Terminology 2 3.1 Terms and definitio
11、ns .2 3.2 Acronyms and abbreviations.4 3.3 Numeric representation.5 4 Device Discovery Process .5 5 System Loops.5 6 IEEE802.11n Modularity .5 7 Basic Parameters.8 8 Frame Formats8 9 Register Sub-Packet Format8 10 Control Field .9 11 Signal Characteristics.10 Standard Improvement Form 11 FIGURES Fig
12、ure 1 Interface layer diagram.1 Figure 2 - One Spatial Stream 1X1 IEEE802.11n .6 Figure 3 - Two Spatial Stream 2X2 IEEE802.11n6 Figure 4 - Two Spatial Stream 2X3 or 3X3 IEEE802.11n7 Figure 5 - Two Spatial Stream 4X4 IEEE802.11n7 JEDEC Standard No. 96A-1 -ii- INTEROPERABILITY AND COMPLIANCE FOR THE R
13、ADIO FRONT END-BASEBAND (RF-BB) INTERFACE STANDARD (JESD96) Foreword This publication provides recommendations for the interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC) for use of JEDEC standard JESD96A in the proposed wireless local area network system IEEE 802.11n.
14、Note that at the time of this publication, the IEEE 802.11n standard has not been approved or published. However, in this publication we assume that systems based on IEEE 802.11n, if it becomes a standard, will be similar to the standards IEEE 802.11a/g, and will use spatial multiplexing with data r
15、ates in excess of 100 Mbps. Therefore, we have developed recommendations for such a system, with these recommendations not dependent on the finer details of the IEEE 802.11n standard. Furthermore, these recommendations should also be applicable to other wireless systems, including IEEE 802.16 and ce
16、llular systems. These recommendations are intended to ensure that multiple RF and baseband IC vendors can design ICs with a common IC interface allowing each of the devices to work with each other. Included are requirements for electrical signaling, link layer state machines and register map definit
17、ions. Introduction The RF to baseband interface specified in the JEDEC standard JESD96A is briefly described as follows. This interface is a high-speed, low latency digital interface that has been defined primarily for wireless local area networking applications but can be used for other RF to BB li
18、nks such as used in metro area networking and wide area networking applications. This interface allows the radio front end of a wireless network controller to be separated from the base-band and MAC device(s) by up to 50 cm. A typical example is to connect a radio front end in the upper (screen) por
19、tion of a laptop computer to a base-band device on the motherboard. Lower power options are also defined for shorter distances. The basic interface consists of three differential signals totaling to six pins. A clock signal must be provided by the FED on one pair of pins along with two pairs of pins
20、 for data transfers from the FED to BED and in the reverse direction. A separate pair is dedicated for either direction. Figure 1 illustrates the pin connections for the RF-BB interface. An optional pair of pins can be assigned for a return clock from the BED to the FED. The interface provides three
21、, concurrent, logical channels for communication: a streaming data channel, a control channel and a register access channel. Each of these channels can be programmed by the BED, subject to the constraints indicated by the FED in its capability registers. The FED determines the clock frequency, while
22、 the BED can select the data frame formats subject to the constraints indicated by the FED in its capability registers. For 802.11n, we make further recommendations concerning the following items: 1) Device discovery process 2) System loops 3) 802.11n modularity 4) Basic configuration 5) Basic param
23、eters 6) Frame formats 7) Register sub-packet format 8) Control field 9) Signal characteristics It is the goal of this I 2) RF-BB Link layer: bits, clock-data synchronization, power modes; 3) RF-BB Transport layer: data types, data framing, data bandwidth, connection to core IC; 4) RF-BB Interface R
24、egisters. The JESD96A document defines a high-speed serial link that enables the bi-directional transfer of data and control information between the FED and BED. Unlike the JESD96A document, however, this I 29 August 2001 Specification. HyperTransport I/O Link Specification Revision 1.03. JESD96A, R
25、adio Front End-Baseband (RF-BB) Interface, February 2006. 2.2 Normative JEP106, Standard Manufactures Identification Code 3 Terminology For the purpose of this standard, the following terms, definitions, acronyms and abbreviations apply. 3.1 Terms and definitions base-band frequencies: Low frequenci
26、es neighboring and including 0 Hz. These frequencies are represented with real In-Phase (I) and Quadrature (Q) parts or together as a complex signal. In this document, the word “base-band” will usually refer to a base-band processor (part of the BED in this interface). common mode voltage: The avera
27、ge voltage level of the two signals on a differential line. deskew: The act of aligning a clock with incoming data so that the clock edge can be used to latch data in the middle of the data eye. frame: A group of serial bits consisting of a Sync Mark, Header, and one or more of the following fields:
28、 1) streaming data, 2) control data, 3) register data, and 4) parity bit. radio: A device or a group of devices that translates the information bandwidth between base-band and the radio frequency portion of the spectrum. Rx-direction: Direction of Receiving from Front End Device to Back End Device.
29、Rx-link: Data link that moves data from Front End Device to Back End Device. TX-direction: Direction of transmitting from the Back End Device to the Front End Device. TX-link: Data link that moves data from Back End Device to Front End Device. little endian: The format in which the least significant
30、 bit (LSB) of a word is transferred first and the most significant bit is transferred last. big endian: The format in which the most significant bit (MSB) of a word is transferred first and the least significant bit is transferred last. JEDEC Standard No. 96A-1 Page 3 3 Terminology (contd) 3.1 Terms
31、 and definitions (contd) TX_IN: Single-ended combination of TX/TXN analog signals received by FED. TX_DATA_VALID (FED): Indication the TX_IN signal contains data for the FED Transport Layer. TX_CLK: Clock signal from FED Link Layer to the FED Transport Layer that has been deskewed for maximum data e
32、ye opening on TX_IN. RX_OUT: Single-ended serial data from the FED Transport Layer to the FED Link Layer which is synchronized with CLK_90. RX_DATA_VALID (FED): Indication that the RX_OUT signal contains data for the FED Link layer. CLK_90: 90-degree-offset clock signal provided by the FED Link Laye
33、r to the FED Transport layer to synchronize outgoing RX_OUT. LINK_REQUEST: Indication that the Transport layer requires FED Link Layer services. This could also serve as a data clock request. DESKEW_REQUEST: Indication that the Transport layer needs the Link to deskew incoming data and clocks. One p
34、ossible reason to send this is because of some CRC error seen in the Transport layer. LINK_STATUS: This signal reports that the Link is ready, or not ready. It is related to DESKEW_STATUS as well. TX_CM_DET: Indication to the FED Link layer from the FED Electrical layer that a minimum active common
35、mode voltage has been detected on the TX/TXN lines. RX_EN: Enables the RX/RXN drivers on the FED Electrical Layer to transmit. CLK_0 (FED): FED: Single-ended zero-phase-offset clock from the FED Link layer for the CLK/CLKN driver in the FED Electrical Layer. CLK_0 (BED): BED: Single-ended clock sign
36、al from the BED Electrical Layer to the BED Link Layer corresponding to CLK/CLKN. CLK_EN: Enables the CLK/CLKN drivers on the FED Electrical Layer to transmit. CLK_DET: Indication to the BED Link layer that the BED Electrical Layer has detected a minimum active common mode voltage on the CLK/CLKN li
37、nes. RX_CM_DET: Indication from the BED Electrical layer to the BED Link Layer that a minimum common mode voltage was detected on the RX/RXN lines. RX_IN: Single-ended analog BED signal corresponding to the received differential RX/RXN signal in the BED Electrical Layer. TX_EN: Enables the TX/TXN dr
38、ivers in the BED Electrical layer to transmit. TX_OUT: Single-ended data to be driven differentially on TX/TXN. JEDEC Standard No. 96A-1 Page 4 3 Terminology (contd) 3.1 Terms and definitions (contd) TX_DATA_VALID (BED): Indication from the BED Transport Layer that TX_OUT contains valid data for the
39、 BED Link Layer. RX_DATA_VALID (BED): Indication that signals from the BED Link layer on RX_IN contains data for the BED Transport Layer. 3.2 Acronyms and abbreviations BED Back-end device. Relative to the RF-BB interface, the BED is the baseband processor. BW Bandwidth CLK, CLKN The Clock different
40、ial pair DDR Double data rate clocking. Data clocked on both the rising and falling edges of the interface clock signal. Def Default Value FED Front-end device. Relative to the RF-BB interface, the FED is the radio frequency device. Flight Delay Propagation time of the signal on a transmission line
41、HDR Header MAC Medium access Control MIMO Multiple Input Multiple Output PHY A Wireless LAN, MAN or PAN physical layer interface. The bottom layer of the JC-61 RF-BB is called “electrical layer”. RF Relating to a Radio Frequency device. RF-BB Relating to the interface between a Radio Frequency devic
42、e and a Baseband processor. Rx Receive RX, RXN The Receive differential pair signals TX, TXN The Transmit differential pair signals Tr Rising or falling transition time. The time it takes to transition from one defined signal level to another. Tx Transmit UI Unit interval or bit interval. For double
43、 data rate clocking, the unit interval is half of a clock cycle. VCM Common mode voltage. JEDEC Standard No. 96A-1 Page 5 3 Terminology (contd) 3.2 Acronyms and abbreviations (contd) WLAN Wireless data packet network in a general sense, including IEEE 802.11, wireless Metropolitan Area Networks, inc
44、luding IEEE 802.16; and wireless Personal Area Networks, including IEEE 802.15. 3.3 Numeric representation The numerical values are in decimal unless indicated otherwise. The values specified in decimal are coded in natural binary unless otherwise stated. 4 Device Discovery Process Let us first cons
45、ider the device discovery process. This process involves the following three steps. In step 1, the FED device number and manufacturer code is read. In step 2, the initialization sequence from the firmware-based driver on the FED is loaded via the BED. In step 3, the FED is controlled as required usi
46、ng Control and Register packet write and reads, as described below. 5 System Loops There are two basic system loops, one for gain control and one for transmit power control. For gain control, the FED is responsible and uses a handshake with the BED via a control word. For transmit power control, the
47、 FED is also responsible, again using a handshake with the BED via control and register words. In this case, initial factory calibration is required. 6 IEEE 802.11n Modularity The proposed standard IEEE802.11n contains several MIMO configurations, some mandatory and some optional. Furthermore, both
48、20 MHz and 40 MHz channels may be used. The MIMO configurations include 1X1 (i.e., 1 transmit and 1 receive antenna), 2X2, 2X3, and 4X4. To implement these, we consider the possible IEEE 802.11n FED configurations using optionally different mixtures of FEDs. These include the following cases: 1x1 2x
49、2 A Pair of 1x1s Integrated 2x2 2x3 A set of 1x1s A set of 1x1 and 2x2 Integrated 2x3 4x4 A set of 1x1s A pair of 2x2s Integrated 4x4 JEDEC Standard No. 96A-1 Page 6 6 IEEE 802.11n Modularity (contd) The basic configuration is 1X1. This consists of an 8 pin interface for a 20 MHz only device, and a 12 pin interface for a 40 MHz device. In both cases the transmit and receive clocks, TxCLK and RxCLK are provided by two pins each. The transmit and receive data, TxDATA and RxDATA, is provided by 2 pins each for the 20
