1、 JEDEC STANDARD Ball Grid Array Pinouts Standardized for 16, 18 and 20-Bit Logic Functions Using a 54 Ball Package JESD75-1 OCTOBER 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC
2、Board of Directors level and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of produc
3、ts, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their a
4、doption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications r
5、epresents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No cla
6、ims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, A
7、rlington, VA 22201-3834, (703)907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2001 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individ
8、ual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada 1-800-854-7179, International (303) 397-7956 Printed in the U.S.A. All rights reserved PLEASE
9、! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 W
10、ilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 75-1 Page 1 BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, and 20-BIT LOGIC FUNCTIONS (From JEDEC Board Ballot JCB-01-71, formulated under the cognizance of the JC-40 Committee on Digital Logic.) 1 Scope This
11、standard defines device pinout for 16/18/20-bit wide buffer, driver, register and transceiver functions. This pinout specifically applies to the conversion of TSSOP-Packaged 16/18/20-bit logic devices to FBGA-packaged devices. The purpose is to provide a pinout standard for 16/18/20-bit logic device
12、s offered in a 54-ball area grid array package. This proposed standard provides an electrical pinout for multiple sources, eliminates confusion, simplifies device specification, and adds ease of use to the new package design. 2 Terms and definitions for the purpose of this document FBGA: Fine-Pitch
13、Ball Grid Array; 5.5mm wide body (MO-205) TSSOP: Thin Shrink Small-Outline Package; 0.5mm lead pitch; 6.1mm wide body (MO-153) JEDEC Standard No. 75-1 Page 2 3 Pinout standard 3.1 Description The following criteria shall be used to convert existing 16/18/20-bit logic device functions offered in 48-
14、and 56- pin packages to devices offered in the 54-ball FBGA package: a) Attributes for the FBGA package shall be,54-Ball, 0.80 mm ball pitch with 5.5mm x 8.0mm body size and 6-row by 9-column ball matrix. b) Device conversion shall be as follows: Bit Count TSSOP Package FBGA Package 16-Bit 48-pin 54
15、-Ball 18/20-Bit 56-pin 54-Ball c) The pinout conversions shall be in accordance with the diagrams shown in section 3.3 and 3.6. 3.2 54-Ball FBGA (MO-205, Variation DD) Figure 1 Pinout configuration JEDEC Standard No. 75-1 Page 3 3 Pinout standard (contd) 3.3 Pin conversion from 48-pin TSSOP to 54-ba
16、ll FBGA. The pin conversion adopts the naming convention of logic devices in 48-pin packages. 6 4744413836333027265 NC* 46434037353229NC* 4 48NC* 424534,392831NC* 253 1NC* 7410,152118NC* 242 NC* 36912141720NC* 1 258111316192223A B C D E F G H J GND Pins: D3, D4, E3, E4, F3, and F4 VDDPins: C3, C4, G
17、3, and G4 Control Pins: A3, A4, J3, and J4 I/O and Signal Pins: A1, A6, B1, B2, B5, B6, C1, C2, C5, C6, D1, D2, D5, D6, E1, E2, E5, E6, F1, F2, F5, F6, G1, G2, G5, G6, H1, H2, H5, H6, J1, and J6 * No Connection Pins: A2, A5, B3, B4, H3, H4, J2, and J5 Figure 2 48 pin TSSOP pin conversion (top view)
18、JEDEC Standard No. 75-1 Page 4 3 Pinout standard (contd) 3.4 Pin conversion from 56-pin TSSOP to 54-ball FBGA. The pin conversion adopts the naming convention of logic devices in 56-pin packages. 6 5249474442403734335 5451484543413836314 56#55505339,4632353029#3 127411,18252227282 3691214161921261 5
19、810131517202324A B C D E F G H J GND Pins: D3, D4, E3, E4, F3, and F4 VDDPins: C3, C4, G3, and G4 Control Pins: A3 and J3 I/O and Signal Pins: A1, A6, B1, B2, B5, B6, C1, C2, C5, C6, D1, D2, D5, D6, E1, E2, E5, E6, F1, F2, F5, F6, G1, G2, G5, G6, H1, H2, H5, H6, J1, and J6 Control or Signal Pin: A2, A5, B3, B4, H3, H4, J2, and J5 # GND or Control Pin: A4 and J4 Figure 3 56 pin TSSOP pin conversion (top view) 4 Reference to other applicable JEDEC standards and publications JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products, MO-205, Variation DD.
