1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R095-97. CFS 96-11-18 Monica L. Poelking B Add limit for linear energy threshold (LET) with no latch-up in section 1.5. Update the boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout.
2、 TVN 06-03-20 Thomas M. Hess C Update boilerplate paragraphs and radiation paragraphs 4.4.4.1 4.4.4.4 to the current MIL-PRF-38535 requirements. - LTG 12-03-22 Thomas M. Hess D To correct switching waveforms input/output test limits to figure 4. Add test equivalent circuits and footnote 5 to figure
3、4. Add paragraph 2.2 for ASTM F1192 document. Delete class M requirements throughout.MAA 13-01-25 Thomas M. Hess REV SHEET REV D SHEET 15 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen DLA LAND AND MARITIME COLUMBUS, O
4、HIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, RADIATION HARDENED, ADVANCED CMOS, Q
5、UADRUPLE S-R LATCH, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 96-05-20 REVISION LEVEL D SIZE A CAGE CODE 67268 5962-96581 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E189-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
6、MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V).
7、A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 96581 01 V X A Federal sto
8、ck class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked wi
9、th the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACTS279 Radiation hardened, quadruple S-R latch, TTL compatible inputs 1.2.3 Device class desi
10、gnator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follow
11、s: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line X CDFP4-F16 16 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted with
12、out license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc DC input voltage range (VIN) -0.3 V dc to V
13、DD + 0.3 V dc DC output voltage range (VOUT) . -0.3 V dc to VDD+ 0.3 V dc DC input current, any one input (IIN). 10 mA Latch-up immunity current (ILU) 150 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, junction-to-case (JC) . See
14、 MIL-STD-1835 Junction temperature (TJ) +175C Maximum power dissipation (PD) . 1.0 W 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VDDOutput voltage range (VOUT). 0.0 V dc to VDDMaximum input rise or fall time at V
15、DD= 4.5 V (tr, tf) 1 ns/V 4/ Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features. 5/ Maximum total dose available (dose rate = 50 300 rads (Si)/s) 1 x 106Rads (Si) Single event phenomenon (SEP): Effective linear energy transfer (LET), no upsets (see 4.4.4.4) 80 MeV/(mg/cm2)
16、6/ Effective linear energy transfer (LET), no latch-up (see 4.4.4.4) 120 MeV/(mg/cm2) 6/ Dose rate upset (20 ns pulse) 1 x 109Rads (Si)/s Latch-up . None Dose rate survivability 1 x 1012Rads (Si)/s 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended opera
17、tion at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise sp
18、ecified. 4/ Derate system propagation delays by difference in rise time to switch point for tror tf 1 ns/V. 5/ Radiation testing is performed on the standard evaluation circuit. 6/ Limits obtained during technology characterization/qualification, guaranteed by design or process, but not production t
19、ested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DS
20、CC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solic
21、itation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT O
22、F DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelph
23、ia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide
24、 for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http:/www.astm.org/ or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of pr
25、ecedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requ
26、irements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herei
27、n. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The termi
28、nal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specifie
29、d on figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2.6 Radiation exposure circuit. The radiat
30、ion exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
31、 electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical t
32、ests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the o
33、ption of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a
34、 “QML“ or “Q“ as required in MIL-PRF-38535. . 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitt
35、ed to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for d
36、evice classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43
37、218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 2/ Unit Min Max High level input voltage VIH All 4.5 V 1, 2, 3 2.25 V M, D, P, L,
38、R, F, G, H 3/ All 1 2.25 All 5.5 V 1, 2, 3 2.75 M, D, P, L, R, F, G, H 3/ All 1 2.75 Low level input voltage VIL All 4.5 V 1, 2, 3 0.8 V M, D, P, L, R, F, G, H 3/ All 1 0.8 All 5.5 V 1, 2, 3 0.8 M, D, P, L, R, F, G, H 3/ All 1 0.8 High level output voltage VOH For all inputs affecting output under t
39、est, VIN= VDDor VSSIOH= -8.0 mA All 4.5 V 1, 2, 3 3.15 V M, D, P, L, R, F, G, H 3/ All 1 34.15 Low level output voltage VOL For all inputs affecting output under test, VIN= VDDor VSSIOL= 8.0 mA All 4.5 V 1, 2, 3 0.4 V M, D, P, L, R, F, G, H 3/ All 1 0.4 Input current high IIH For input under test, V
40、IN= VDDFor all other inputs, VIN= VDDor VSSAll 5.5 V 1, 2, 3 +1.0 A M, D, P, L, R, F, G, H 3/ All 1 +1.0 Input current low IIL For input under test, VIN= VSSFor all other inputs, VIN= VDDor VSSAll 5.5 V 1, 2, 3 -1.0 A M, D, P, L, R, F, G, H 3/ All 1 -1.0 Output current (source) IOH4/ For output unde
41、r test, VOUT= VDD - 0.4 V VIN= VDDor VSSAll 4.5 V and 5.5 V 1, 2, 3 -12.0 mA M, D, P, L, R, F, G, H 3/ All 1 -12.0 Output current (sink) IOL4/ For output under test, VOUT= 0.4 V VIN= VDDor VSSAll 4.5 V and 5.5 V 1, 2, 3 12.0 mA M, D, P, L, R, F, G, H 3/ All 1 12.0 Quiescent supply current IDDQVIN= V
42、DDor VSSAll 5.5 V 1, 2, 3 10.0 A M, D, P, L, R, F, G, H 3/ All 1 10.0 Quiescent supply current delta, TTL input levels IDDQ5/ For input under test, VIN= VDD- 2.1 V For all other inputs, VIN= VDDor VSSAll 5.5 V 1, 2, 3 1.6 mA M, D, P, L, R, F, G, H 3/ All 1 1.6 See footnotes at end of table. Provided
43、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96581 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Sy
44、mbol Test conditions 1/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 2/ Unit Min Max Short circuit output current IOS6/ 7/ VOUT= VDDand VSSAll 5.5 V 1, 2, 3 200 mA Input capacitance CINf = 1 MHz See 4.4.1c All 0.0 V 4 15.0 pF Output capacitance COUTf = 1 MHz See 4
45、.4.1c All 0.0 V 4 15.0 pF Switching power dissipation PSW8/ CL= 50 pF, per switching output All 4.5 V and 5.5 V 4, 5, 6 2.1 mW/ MHz M, D, P, L, R, F, G, H 3/ All 4 2.1 Functional test 9/ VIH= 0.5 VDD, VIL= 0.8 V See 4.4.1b All 4.5 V and 5.5 V 7, 8 L H M, D, P, L, R, F, G, H 3/ All 7 L H Propagation
46、delay time, mS to mQ tPLH110/ CL= 50 pF minimum See figure 4 All 4.5 V and 5.5 V 9, 10, 11 1.0 15.0 ns M, D, P, L, R, F, G, H 3/ All 9 1.0 15.0 tPHL110/ CL= 50 pF minimum See figure 4 All 4.5 V and 5.5 V 9, 10, 11 1.0 18.0 M, D, P, L, R, F, G, H 3/ All 9 1.0 18.0 Propagation delay time, mR to mQ tPH
47、L210/ CL= 50 pF minimum See figure 4 All 4.5 V and 5.5 V 9, 10, 11 1.0 17.0 ns M, D, P, L, R, F, G, H 3/ All 9 1.0 17.0 mS or mR pulse width, low twCL= 50 pF minimum See figure 4 All 4.5 V and 5.5 V 9, 10, 11 8.0 ns M, D, P, L, R, F, G, H 3/ All 9 8.0 1/ Each input/output, as applicable, shall be te
48、sted at the specified temperature, for the specified limits, to the tests in table IA herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the IDDQand IDDQtests, the output terminals shall be open. When performing the IDDQand IDDQtests, the current meter shall be placed in the circuit such that all current flows through the meter. 2/ For negative and positive voltage and current values, the sign designates the potential difference in reference to VSSand the direction of current flow, respectively; and the absolute value
