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    DLA SMD-5962-95615 REV C-2001 MICROCIRCUIT LINEAR 8-CHANNEL 12-BIT SERIAL DATA ACQUISITION SYSTEM MONOLITHIC SILICON《8通道 12-BIT连续的数据获得系统硅单片电路线型微电路》.pdf

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    DLA SMD-5962-95615 REV C-2001 MICROCIRCUIT LINEAR 8-CHANNEL 12-BIT SERIAL DATA ACQUISITION SYSTEM MONOLITHIC SILICON《8通道 12-BIT连续的数据获得系统硅单片电路线型微电路》.pdf

    1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R106-96. sbr 96-04-16 M. A. Frye B Changes in accordance with NOR 5962-R255-97. drw 97-03-31 Raymond Monnin C Change the limit of bipolar zero error test, table I, sheet 5. Editorial changes throughout. - drw 0

    2、1-09-20 Raymond Monnin REV SHET REV C C SHET 15 16 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Sandra Rooney COLUMBUS, OHIO 43216 http:/www.dscc.

    3、dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-CHANNEL, 12-BIT SERIAL, DATA ACQUISITION SYSTEM, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-03-27 MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 672

    4、68 5962-95615 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E276-01 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SU

    5、PPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and le

    6、ad finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95615 01 M L A Federal stock class designator RHA designa

    7、tor (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator

    8、. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit funct

    9、ion 01 AD7890-10 8-channel, 12-bit serial, data acquisition system 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-

    10、STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Pac

    11、kage style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking perm

    12、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VDDto AGND . -0.3 V dc to +7 V dc VDDto DGND . -0.3 V dc to +7 V dc Analog input

    13、 voltage to AGND. 17 V dc Reference input voltage to AGND . -0.3 V dc to VDD+ 0.3 V dc Digital input voltage to DGND -0.3 V dc to VDD+ 0.3 V dc Digital output voltage to DGND -0.3 V dc to VDD+ 0.3 V dc Junction temperature (TJ) +150C Power dissipation (PD). 450 mW Thermal resistance, junction-to-amb

    14、ient (JA) . 70C/W Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Lead temperature (soldering, 10 seconds) +300C 1.4 Recommended operating conditions. Ambient operating temperature range. -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The fol

    15、lowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited

    16、 in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS D

    17、EPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, P

    18、hiladelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has

    19、been obtained. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

    20、ICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified

    21、herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class

    22、 level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines.

    23、 The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Ideal input/output table. The ideal input/output table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirra

    24、diation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requiremen

    25、ts shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the

    26、entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking

    27、 for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535,

    28、appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from

    29、a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V,

    30、 the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall

    31、 be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, a

    32、ppendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the revie

    33、wer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

    34、DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Sign

    35、al to noise + distortion ratio SNR fIN= 10 kHz sine wave, fSAMPLE= 100 kHz VDD= +4.75 V dc 1, 2, 3 01 70 dB Total harmonic distortion THD fIN= 10 kHz sine wave, fSAMPLE= 100 kHz VDD= +4.75 V dc 1, 2, 3 01 77 dB Peak harmonic or spurious distortion PHN fIN= 10 kHz sine wave, fSAMPLE= 100 kHz 1, 2, 3

    36、01 78 dB Channel-to-channel isolation CI fIN= 10 kHz sine wave, VDD= +4.75 V dc 1, 2, 3 01 80 dB Resolution RES 1, 2, 3 01 12 Bits Minimum resolution for which no missing codes are guaranteed MRES 1, 2, 3 01 12 Bits Relative accuracy RA 1, 2, 3 01 1 LSB Differential nonlinearity DNL 1, 2, 3 01 1 LSB

    37、 Positive full-scale error PFSE 1, 2, 3 01 2.5 LSB Full-scale error match 2/ FSE 1, 2, 3 01 2 LSB Negative full-scale error NFSE VDD= +4.75 V dc 1, 2, 3 01 2 LSB Bipolar zero error BZE 1, 2, 3 01 5 LSB Bipolar zero error match BZEM 1, 2, 3 01 2 LSB Input voltage range VIN1, 2, 3 01 -10 +10 V Input r

    38、esistance RIN1, 2, 3 01 20 k Mux out output voltage range VOUT1, 2, 3 01 0 2.5 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, O

    39、HIO 43216-5000 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Mux out output resistance ROUT1, 2, 3 01 3 5 k SHA IN input

    40、voltage range VSIN1, 2, 3 01 0 2.5 V SHA IN input current ISINVSIN= 2.49 V 1, 2, 3 01 -50 +50 nA REF IN input voltage range VRIN1, 2, 3 01 2.375 2.625 V Input impedance RRINResistor connected to internal reference node 1, 2, 3 01 1.6 k REF OUT voltage VROUT1 01 2.49 2.510 V 2, 3 2.475 2.525 Logic in

    41、put high voltage VINHVDD= 5 V 5% 1, 2, 3 01 2.4 V Input low voltage VINLVDD= 5 V 5% 1, 2, 3 01 0.8 V Input current IIN VIN= 0 V to VDD1, 2, 3 01 -10 +10 A Output high voltage VOHISOURCE= 200 A, VDD= 4.75 V 1, 2, 3 01 4 V Output low voltage VOLISINK= 1.6 mA, VDD= 4.75 V 1, 2, 3 01 0.4 V Conversion ti

    42、me 3/ tCONVfCLKIN= 2.5 MHz, VDD= 4.75 V, MUX OUT connected to SHA IN 9, 10, 11 01 5.9 s Supply voltage VDD5% for specified performance 1, 2, 3 01 5 V Supply current 4/ IDDLogic inputs = 0 V or VDD1, 2, 3 01 10 mA Power dissipation PD1, 2, 3 01 50 mW See footnotes at end of table. Provided by IHSNot

    43、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Sym

    44、bol Conditions 1/, 3/, 5/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Master clock frequency 6/ fCLKIN9, 10, 11 01 0.1 2.5 MHz Master clock input low time tCLKINL9, 10, 11 01 0.3 x tCLKIN ns Master clock input high time tCLKINH9, 10, 11 01 0.3 x tCLKIN

    45、ns Digital output rise time 7/ tR9, 10, 11 01 25 ns Digital output fall time 7/ tF9, 10, 11 01 25 ns Conversion time tCONVERT9, 10, 11 01 5.9 s CONVST pulse width tCST9, 10, 11 01 100 ns RFS low to SCLK falling edge t19, 10, 11 01 tCLKINH+ 50 ns RFS low to valid delay 8/ t29, 10, 11 01 25 ns SCLK hi

    46、gh pulse width t39, 10, 11 01 tCLKINHns SCLK low pulse width t49, 10, 11 01 tCLKINLns SCLK rising edge to data valid delay 8/ t59, 10, 11 01 20 ns SCLK rising edge to RFS delay t69, 10, 11 01 40 ns Bus relinquish time after rising edge of SCLK 9/ t79, 10, 11 01 50 ns TFS low to SCLK falling edge t89

    47、, 10, 11 01 0 tCLKIN+ 50 ns Data valid to TFS falling edge setup time (A2 address bit) t99, 10, 11 01 0 ns Data valid to SCLK falling edge setup time t109, 10, 11 01 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

    48、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95615 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/, 3/, 5/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Data valid to SCLK falling edge hold time t119, 10, 11 01 10 ns TFS to SCLK falling edge hold time t129, 10, 11 01 20 ns RFS low to SCLK falling edge setup time t139, 10, 11 01 20 ns RFS low to data valid delay 8/ t149, 10, 11 01 40 ns SCLK high pulse widt


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