1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device types 05 through 10. Added case outlines X, Z, and T. Redrew entire document. 96-08-23 K. A. Cottongim B Added device types 11 through 13. Added case outline U. 96-10-22 K. A. Cottongim C Made changes in accordance with NOR 5962-R289
2、-97. -sld 97-04-28 K. A. Cottongim D Table I; Changed the max limit for the operating supply current test ICCfor device types 05-10 from 130 mA to 135 mA. Table I; Changed the max limit for data retention current (ICCDR1) for device types 05-10 from 3.0 mA to 7.0 mA. Add vendor cage 88379 for device
3、 types 11, 12, and 13 per letter dated 1 MAY 1997. -sld 98-02-18 E Add device type 14. 98-06-22 K. A. Cottongim F Changes to case outlines U and X. 99-04-30 K. A. Cottongim G Add: note to paragraph 1.2.2 and table I, conditions. Add device types 15 through 27, case outlines M, N, and 9, vendor CAGE
4、code 0EU86, condition D to paragraphs 4.2.a.1 and 4.3.3.b.1. Changes to table I and dimensions to case outlines T, U, Y, and Z. Table I, add note 3 to CINand COUT. 01-02-08 Raymond Monnin H Table I; Changed the IOLfrom 8 mA to 6 mA for device types 07-14 and 21-27 for the VOLtest. Added device types
5、 28, 29, and 30. Editorial changes throughout. -sld 04-05-28 Raymond Monnin J Add new case outline 7. gc 08-08-04 Robert M. Heber K Updated drawing paragraphs. -sld 12-04-02 Charles F. Saffle REV SHEET REV K K K K K K K K K K K K K K K K K K SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3
6、2 REV STATUS REV K K K K K K K K K K K K K K OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael C. Jones THIS DRAWING IS AVAILABLE FO
7、R USE BY ALL DEPARTMENTS APPROVED BY Kendall A. Cottongim MICROCIRCUIT, MEMORY, DIGITAL, SRAM, 512K x 8-BIT, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-11-07 AMSC N/A REVISION LEVEL K SIZE A CAGE CODE 67268 5962-95613 SHEET 1 OF 32 DSCC FORM 2233 APR 97 596
8、2-E296-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95613 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five p
9、roduct assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The
10、PIN shall be as shown in the following example: 5962 - 95613 01 H X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) des
11、ignator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 1/ 2/ Generic number Circ
12、uit function Data retention Access time 01 AS5C4009-120, WMS512K8-120 512K x 8 bit SRAM Yes 120 ns 02 AS5C4009-100, WMS512K8-100 512K x 8 bit SRAM Yes 100 ns 03 AS5C4009-85, WMS512K8-85 512K x 8 bit SRAM Yes 85 ns 04 AS5C4009-70, WMS512K8-70 512K x 8 bit SRAM Yes 70 ns 05 ACT-S512K8N-055, AS5C512K8-
13、55, WMS512K8-55 512K x 8 bit SRAM Yes 55 ns 06 ACT-S512K8N-045, AS5C512K8-45, WMS512K8-45 512K x 8 bit SRAM Yes 45 ns 07 ACT-S512K8N-035, AS5C512K8-35, WMS512K8-35 512K x 8 bit SRAM Yes 35 ns 08 ACT-S512K8N-025, AS5C512K8-25, WMS512K8-25 512K x 8 bit SRAM Yes 25 ns 09 ACT-S512K8N-020, AS5C512K8-20,
14、WMS512K8-20 512K x 8 bit SRAM Yes 20 ns 10 ACT-S512K8N-017, AS5C512K8-17, WMS512K8-17 512K x 8 bit SRAM Yes 17 ns 11 ACT-S512K8M-045, AS5C512K8-45, WMS512K8M-45 512K x 8 bit SRAM Yes 45 ns 12 ACT-S512K8M-035, AS5C512K8-35, WMS512K8M-35 512K x 8 bit SRAM Yes 35 ns 13 ACT-S512K8M-025, AS5C512K8-25, WM
15、S512K8M-25 512K x 8 bit SRAM Yes 25 ns 14 WMS512K8-15 512K x 8 bit SRAM Yes 15 ns 15 AS5C4009-120L, WMS512K8L-120 512K x 8 bit SRAM Yes 120 ns 16 AS5C4009-100L, WMS512K8L-100 512K x 8 bit SRAM Yes 100 ns 17 AS5C4009-85L, WMS512K8L-85 512K x 8 bit SRAM Yes 85 ns 18 AS5C4009-70L, WMS512K8L-70 512K x 8
16、 bit SRAM Yes 70 ns 19 AS5C512K8-55L, WMS512K8L-55 512K x 8 bit SRAM Yes 55 ns 20 AS5C512K8-45L, WMS512K8L-45 512K x 8 bit SRAM Yes 45 ns 21 AS5C512K8-35L, WMS512K8L-35 512K x 8 bit SRAM Yes 35 ns 22 AS5C512K8-25L, WMS512K8L-25 512K x 8 bit SRAM Yes 25 ns 23 AS5C512K8-20L, WMS512K8L-20 512K x 8 bit
17、SRAM Yes 20 ns 24 AS5C512K8-17L, WMS512K8L-17 512K x 8 bit SRAM Yes 17 ns 25 AS5C512K8-45L 512K x 8 bit SRAM Yes 45 ns 26 AS5C512K8-35L 512K x 8 bit SRAM Yes 35 ns 27 AS5C512K8-25L 512K x 8 bit SRAM Yes 25 ns 28 AS5C512K-12L, WMS512K8L-12 512K x 8 bit SRAM Yes 12 ns 29 AS5C512K-12, WMS512K8-12 512K
18、x 8 bit SRAM No 12 ns 30 WMS512K8U-12 512K x 8 bit SRAM Yes 12 ns 1/ Due to the nature of the 4 transistor design of the die used in these device types, topologically pure testing is important, particularly for high reliability applications. The device manufacturer should be consulted concerning the
19、ir testing methods and algorithms. 2/ Device types and case outlines may be similar to the device types and case outlines listed on SMD 5962-95600. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95613 DLA LA
20、ND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 3 DSCC FORM 2234 APR 97 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certifica
21、tion as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class
22、level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer spec
23、ified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be sp
24、ecified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. Th
25、is product may have a limited temperature range. 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style M See figure 1 32 Leadless chip carrier, ceramic N See figure 1 36 Leadless chip carrier, c
26、eramic T See figure 1 32 SOJ, ceramic, evolutionary pinout U See figure 1 36 Flat pack, ceramic, with or without pedestal X See figure 1 36 Flat pack, ceramic, with non-conductive tie bar, with or without pedestal Y See figure 1 32 DIP, ceramic, single cavity Z See figure 1 36 SOJ, ceramic 9 See fig
27、ure 1 32 Flat pack, ceramic 7 See figure 1 36 SOJ, ceramic 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc Signal voltage range (Vg) . -0.5 V dc to VCC+ 0.5 V dc Power dissipation (PD) 1.1
28、 W maximum Storage temperature range . -65 C to +150 C Lead temperature (soldering, 10 seconds) . +300 C Junction temperature (TJ) . 150 C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affe
29、ct reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95613 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Suppl
30、y voltage range (VCC) . +4.5 V dc to +5.5 V dc Input low voltage range (VIL) . -0.3 V dc to +0.8 V dc Input high voltage range (VIH) . +2.2 V dc to VCC+0.3 V dc Output low voltage, maximum (VOL) +0.4 V dc Output high voltage, minimum (VOH) . +2.4 V dc Ambient operating temperature range (TA) . -55 C
31、 to +125 C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation o
32、r contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS
33、 MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5
34、094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUI
35、REMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management
36、(QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan
37、 shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in a
38、ccordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
39、,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95613 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 5 DSCC FORM 2234 APR 97 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5. 3.2.5 Block diagram. The block diagram shall be as specified on
40、figure 6. 3.2.6 Output load circuit. The output load circuit used to test product shall be equivalent to the circuit specified on figure 7. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall
41、apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.6 Marking of device(s). Marking of device(s) shall be in acco
42、rdance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintai
43、n the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained
44、under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of
45、compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of m
46、icrocircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, o
47、r function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B or D. The test circuit shall be maintained by the manufacturer under document revision
48、level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TAas specified in accordance with table 1 of method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provid
