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    DLA SMD-5962-93155 REV C-2012 MICROCIRCUIT HYBRID MEMORY 256K X 8-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY.pdf

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    DLA SMD-5962-93155 REV C-2012 MICROCIRCUIT HYBRID MEMORY 256K X 8-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY.pdf

    1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added case outline Y. Redrew entire document 97-01-14 K. Cottongim B Update drawing to the current requirements of MIL-PRF-38534. 05-08-08 Raymond Monnin C Updated drawing paragraphs. -sld 12-07-11 Greg Cecil REV SHEET REV C C C SHEET 15 16 17 RE

    2、V STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve Duncan DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael Jones THIS DRAWING IS AVAILABLE FOR USE BY A

    3、LL DEPARTMENTS APPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, 256K X 8-BIT, ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-03-26 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-93155 SHEET 1 OF 17 DSCC FORM

    4、 2233 APR 97 5962-E263-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing

    5、documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PI

    6、N. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 93155 01 H X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness ass

    7、urance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number

    8、Circuit function Access time 01 WE-256K8-200CQ EEPROM, 256K x 8-bit 200 ns 02 WE-256K8-150CQ EEPROM, 256K x 8-bit 150 ns 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF

    9、-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H

    10、Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temp

    11、erature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that cla

    12、ss. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers

    13、 internal, QML certified flow. This product may have a limited temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3

    14、 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 32 Dual-in-line, dual cavity Y See figure 1 32 Dual-in-line, dual cavity 1.2.5 Lead finish. The lead finish

    15、 shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.6 V dc to +6.25 V dc Input voltage range -0.6 V dc to +6.25 V dc Power dissipation (PD) . 1.6 W Storage temperature range -65 C to +150 C Lead temperature (soldering, 10 seconds) +300 C Thermal re

    16、sistance junction-to-case (qJC) 28 C/W Data retention 10 years minimum 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Input low voltage range (VIL) . -0.3 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+ 0.3 V dc Output voltage, high minim

    17、um (VOH) . +2.4 V dc Output voltage, low maximum (VOL) +0.45 V dc Case operating temperature range (TC) -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent spec

    18、ified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircui

    19、ts. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/dla.mil/quicksearch/ or from t

    20、he Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, s

    21、upersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo r

    22、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for devi

    23、ce classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may elimi

    24、nate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device c

    25、lass. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal con

    26、nections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4, 5, 6, and 7. 3.2.5 Block diagram. The block diagram shall be as specified on figure 8. 3.3 Electr

    27、ical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups s

    28、pecified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be m

    29、arked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Al

    30、so, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7

    31、Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performance requirements of MIL-

    32、PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-

    33、PRF-38534 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

    34、DRAWING SIZE A 5962-93155 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition

    35、D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as a

    36、pplicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TAas specified in accordance with table I of method 1015 of MIL-STD-883. (3) Prior to burn-in all devices shall be programmed with a 00 hex data pattern to the entire memory array. The resulting pattern shall be ve

    37、rified before and after burn-in. Devices having bits not in the proper state after burn-in shall constitute a device failure and shall not be delivered. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-i

    38、n are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE

    39、 I. Electrical performance characteristics. Test Symbol Conditions 1/ -55 C TC +125 C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max DC PARAMETERS Supply current ICCCS = OE = VIL, WE = VIH, I/O 0 through I/O 7 = open, inputs = VCC= +5

    40、.5 V dc, A0 through A17 change at 5 MHz 1,2,3 01,02 180 mA Standby current ISB CS = VCC, I/O 0 through I/O 7 = open, inputs = VCC= +5.5 V dc, A0 through A17 change at 5 MHz 1,2,3 01,02 10 mA Input leakage current ILIVIN= VSSto VCC1,2,3 01,02 80 mA Output leakage current ILOVOUT= VSSto VCC, CS = VIH1

    41、,2,3 01,02 80 mA Input low voltage VIL1,2,3 01,02 0.8 V Input high voltage VIH1,2,3 01,02 2.0 V Output low voltage VOLIOL= +2.1 mA, VCC= +4.5 V 1,2,3 01,02 0.45 V Output high voltage VOHIOH= -400 mA, VCC= +4.5 V 1,2,3 01,02 2.4 V FUNCTIONAL TESTING Functional tests See 4.3.1c 7,8A,8B 01,02 DYNAMIC C

    42、HARACTERISTICS Input capacitance CINVIN= 0 V dc 2/ 4 01,02 90 pF Output capacitance COUTVOUT= 0 V dc 2/ 4 01,02 120 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA

    43、LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C TC +125 C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit M

    44、in Max READ CYCLE AC TIMING CHARACTERISTICS Read cycle time tRCSee figure 4. 9,10,11 01 02 200 150 ns Address access time tACCSee figure 4. 9,10,11 01 02 200 150 ns Chip select access time tACSSee figure 4. 9,10,11 01 02 200 150 ns Output hold from address change OE or CS tOHSee figure 4. 9,10,11 01

    45、,02 10 ns Output enable to output valid tOESee figure 4. 9,10,11 01 02 100 85 ns BYTE WRITE AC TIMING CHARACTERISTICS Address setup time tASSee figure 5. 9,10,11 01,02 30 ns Write pulse width tWPSee figure 5. 9,10,11 01 02 200 150 ns Chip select setup time tCSSee figure 5. 9,10,11 01,02 0 ns Address

    46、 hold time tAHSee figure 5. 3/ 9,10,11 01,02 50 ns Data valid to end of write tDVSee figure 5. 9,10,11 01,02 70 ns Output enable setup time tOESSee figure 5. 9,10,11 01,02 30 ns Data hold time tDHSee figure 5. 9,10,11 01,02 0 ns Output enable hold time tOEHSee figure 5. 9,10,11 01,02 0 ns Chip selec

    47、t hold time tCSHSee figure 5. 9,10,11 01,02 0 ns Write pulse width high tWPHSee figure 5. 9,10,11 01,02 50 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93155 DLA LAND AND

    48、MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C TC +125 C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max PAGE MODE WRITE AC TIMING CHARACTERISTICS Data setup time tDSSee figure 6. 9,10,11 01,02 100 ns Data hold time tDHSee figure 6. 9,10,11 01,02 10 ns Write pulse width


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