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    DLA SMD-5962-92105 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 8 - MACROCELL ELECTRICALLY PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON.pdf

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    DLA SMD-5962-92105 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 8 - MACROCELL ELECTRICALLY PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Reformatted with updated boilerplate for 5 year review. lhl 12-03-19 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV A A SHET 15 16 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6

    2、7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED

    3、 BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 8 MACROCELL ELECTRICALLY PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON DRAWING APPROVAL DATE 92-10-13 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-92105 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E188-12 Provided by IHSNot for ResaleNo r

    4、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92105 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of

    5、high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 P

    6、IN. The PIN is as shown in the following example: 5962 - 92105 01 M L A Federal stock class designator RHAdesignator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V

    7、RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.

    8、2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 MD85C224-50/B 8-macrocell EPLD 15 ns 02 MD85C224-66/B 8-macrocell EPLD 12 ns 1.2.3 Device class designator. The device class designator is a single letter identif

    9、ying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38

    10、535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, and V or MI

    11、L-PRF-38535, appendix A for device class M. _ 1/ Lid shall be transparent to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92105 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-

    12、3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage to ground potential (VCC) . -2.0 V dc to +7.0 V dc DC input voltage range . -0.5 V dc to VCC+0.5 V dc Maximum power dissipation 1.5 W 3/ Lead temperature (soldering, 10 seconds). +275C Thermal resista

    13、nce, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ). +150C Storage temperature range -65C to +150C Temperature under bias -55C to +125C Endurance . 25 erase/write cycles (minimum) Data retention . 10 years (minimum) 1.4 Recommended operating conditions. Supply voltage range (VCC) +

    14、4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C Input rise time (tR) . 500 ps maximum Input fall time (tF) . 500 ps maximum 2. APPLICABLE DOCUM

    15、ENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFE

    16、NSE SPECIFICATION MIL-M-38510 - Microcircuits, General Specification for. MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outli

    17、nes. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, B

    18、uilding 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Must withstand the added PDdue to short circuit test; e.g., ISC. Provided by

    19、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92105 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part

    20、 of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of this document are available onlin

    21、e at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be availab

    22、le in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations

    23、unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification i

    24、n the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The d

    25、esign, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The t

    26、erminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required i

    27、n screening (see 4.2 herein) or qualification conformance inspection, groups A, B, or C (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any al

    28、tered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteris

    29、tics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined i

    30、n table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on t

    31、he device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certificati

    32、on mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR

    33、CUIT DRAWING SIZE A 5962-92105 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requir

    34、ements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to list

    35、ing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certific

    36、ate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Ma

    37、ritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain

    38、the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit

    39、group number 042 (see MIL-PRF-38535, appendix A). 3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.11.1 Unprogrammed devi

    40、ce delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.11.2 Manufacturer programmed device delivered to the user. All

    41、 testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.12 Processing EPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufactu

    42、rer prior to delivery. 3.12.1 Erasure of EPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.12.2 Programmability of EPLDs. When specified, devices shall be programmed to the specified pattern using the procedures and characteristi

    43、cs specified in 4.5. 3.12.3 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.5 herein) to the specified pattern or erased (see 4.4 herein). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verif

    44、y that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.13 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test sh

    45、all be done only for initial characterization and after any design or process changes which may affect the reprogrammability of the device. This test shall consist of 25 program/erase cycles on 25 devices with the following conditions: a. All devices selected for testing shall be programmed in accor

    46、dance with 3.2.3.1 herein. b. Verify pattern (see 3.12.3). c. Erase (see 3.12.1). d. Verify pattern erasure (see 3.12.3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92105 DLA LAND AND MARITIME COLUMBUS,

    47、OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C 4.5 V dc VCC5.5 V dc unless otherwise specified Group A subgroupsDevice type Limits Unit Min Max High level input voltage 2/ VIH1, 2, 3 All 2.0 VCC+

    48、0.3 3/ V Low level input voltage 2/ VIL1, 2, 3 All -0.3 3/ 0.8 V Low level input voltage 4/ VOLIOL= 12 mA VCC= minimum 1, 2, 3 All 0.5 V High level TTL output voltage VOHIOL= -4 mA VCC= minimum 1, 2, 3 All 2.4 V Input leakage current ILVCC= maximum GND VIN VCC1, 2, 3 All 10 A Three-state output off current 3/ IOZVCC= maximum GND VOUT VCC1, 2, 3 All 10 A Output short circuit current 3/ 5/ ISCVCC= maximum VOUT= 0.5 V 1, 2, 3 All -30 -160 mA VCCsupply current 6/ ICCVCC= maximum VIN = VCCor GND No load, input frequency = 1 MHz Device program as an 8-bit counter, nonturbo mode 1, 2, 3 All 10 mA


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