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    DLA SMD-5962-91757 REV B-2009 MICROCIRCUIT MEMORY DIGITAL CMOS 256 X 8 PARALLEL SYNCHRONOUS FIFO MONOLITHIC SILICON.pdf

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    DLA SMD-5962-91757 REV B-2009 MICROCIRCUIT MEMORY DIGITAL CMOS 256 X 8 PARALLEL SYNCHRONOUS FIFO MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to reflect current requirements. Editorial changes throughout. - gap 01-03-14 Raymond Monnin B Update drawing to current requirements. Editorial changes throughout. tcr 09-06-08 Joseph Rodenbeck REV SHET REV B B B B B B B B B SHEET

    2、 15 16 17 18 19 20 21 22 23 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tuan Nguyen DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING

    3、IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-11-18 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 256 X 8 PARALLEL SYNCHRONOUS FIFO, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-91757 SHEET 1

    4、OF 23 DSCC FORM 2233 APR 97 5962-E324-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE

    5、1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a

    6、choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91757 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see

    7、 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are mar

    8、ked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 72200L20 256 X 8 CMOS Parallel Synchronous FIFO 20 ns 1.2.3 Device class desig

    9、nator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, ap

    10、pendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line 1.2.5 Lead finish. The lead finish is a

    11、s specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 432

    12、18-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Terminal voltage with respect to ground . -0.5 V dc to +7.0 V dc DC output current 50 mA Storage temperature range . -65C to +135C Maximum power dissipation (PD) 1.25 W Lead temperature (soldering, 10 seconds) +2

    13、60C Thermal resistance, junction-to-case (JC): See MIL-STD-1835 Junction temperature (TJ). +175C 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V dc to 5.5 V dc Supply voltage (GND) . 0 V Input high voltage (VIH) 2.2 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum Case oper

    14、ating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are t

    15、hose cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case

    16、 Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Aven

    17、ue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

    18、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless

    19、 otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Bou

    20、levard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of pre

    21、cedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requi

    22、rements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described her

    23、ein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-

    24、PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The tr

    25、uth table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full c

    26、ase operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the

    27、manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for d

    28、evice classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The complian

    29、ce mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein).

    30、 For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall

    31、affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V i

    32、n MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUP

    33、PLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Unit unless otherwise specified Min Max Input leakage current ILI0.4 V VIN VCC1, 2, 3 -

    34、10 +10 A Output leakage current ILOOE VIH, 0.4 VOUT VCC1, 2, 3 -10 +10 A Output high voltage VOHIOH= -2 mA 1, 2, 3 2.4 V Output low voltage VOLIOL= 8 mA 1, 2, 3 0.4 V Active power supply current ICCf = 20 MHz, outputs open 1, 2, 3 160 mA Input capacitance CINVIN= 0 V, f = 1.0 MHz, TA= +25C, see 4.4.

    35、1e 4 10 pF Output capacitance COUTVOUT= 0 V, f = 1.0 MHz, with output deselected ( OE = high), TA= +25C, see 4.4.1e 4 10 pF Functional tests See 4.4.1c 7, 8A, 8B Clock cycle frequency fs 9, 10, 11 50 MHz Data access time tA9, 10, 11 2 12 ns Clock cycle time tCLK9, 10, 11 20 ns Clock high time tCLKH9

    36、, 10, 11 8 ns Clock low time tCLKL9, 10, 11 8 ns Data setup time tDS9, 10, 11 5 ns First read latency time tFRLCL= 30 pF, input pulse levels = GND to 3.0 V; input rise/fall times = 3 ns; input timing reference levels = 1.5 V; output timing reference levels =1.5 V; see figure 3 and 4 9, 10, 11 1/ ns

    37、Data hold time tDH9, 10, 11 1 ns Enable setup time tENS9, 10, 11 5 ns Enable hold time tENH9, 10, 11 1 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CE

    38、NTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limit Unit unless otherwise specified Min Max Reset pulse width 2/ tRSCL= 30 pF,

    39、input pulse levels = GND 9, 10, 11 20 ns to 3.0 V; input rise/fall times = 3 ns; Reset setup time tRSSinput timing reference levels = 1.5 V; 9, 10, 11 20 ns output timing reference levels = 1.5 V; Reset recovery time tRSRsee figure 3 and 4 9, 10, 11 20 ns Reset to flag and output time tRSF9, 10, 11

    40、20 ns Output enable to output in low Z 3/tOLZ9, 10, 11 0 ns Output enable to output valid tOE9, 10, 11 3 10 ns Output enable to output in high Z 3/ tOHZ9, 10, 11 3 10 ns Write clock to full flag tWFF9, 10, 11 12 ns Read clock to empty flag tREF9, 10, 11 12 ns Read clock to almost-empty flag tAE9, 10

    41、, 11 12 ns Write clock to almost-full flag tAF9, 10, 11 12 ns Skew time between read clock and write clock for empty flag & full flag tSKEW19, 10, 11 8 ns Skew time between read clock and write clock for almost-empty flag & almost-full flag tSKEW29, 10, 11 35 ns 1/ When tSKEW1 the minimum limit, tFR

    42、L(maximum) = tCLK+ tSKEW1. When tSKEW1 the minimum limit, tFRL(maximum) = either 2tCLK+ tSKEW1or tCLK+ tSKEW1. The latency timing applies only at the empty boundary ( EF = LOW). 2/ Pulse widths less than the minimum values specified are not allowed. 3/ If not tested, shall be guaranteed to the limit

    43、s specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type All Case outli

    44、ne X Terminal number Terminal symbol 1 D4 2 D3 3 D2 4 D1 5 D0 6 AF 7 AE 8 GND 9 RCLK 10 REN 11 OE 12 EF 13 FF 14 Q0 15 Q1 16 Q217 Q3 18 Q4 19 Q5 20 Q6 21 Q7 22 VCC23 WCLK 24 WEN 25 RS 26 D7 27 D6 28 D5 FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitt

    45、ed without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 No. of words in FIFO FF AF AE EF 0 H H L L 1 to 7 H H L H 8 to 248 H H H H 249 TO 255 H L H H 256 L L H H FIGURE 2.

    46、Truth table. Note: CL= load capacitance and includes jig and probe capacitance. AC test conditions: Input pulse levels GND to 3.0V Input rise/fall times 3ns Input timing reference levels 1.5V Output reference levels 1.5V FIGURE 3. Output load circuit. Provided by IHSNot for ResaleNo reproduction or

    47、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted w

    48、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 FIGURE 4. Timing waveforms continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91757 DEFENSE SUPPLY CENTER COLUMB


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