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    DLA SMD-5962-91584 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

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    DLA SMD-5962-91584 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Reformatted with updated boilerplate for 5 year review. lhl 12-04-24 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A A SHEET 15 16 17 18 19 20 REV STATUS REV A A A A A A A A A A A A A A OF SHE

    2、ETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Ke

    3、nneth Rice APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON DRAWING APPROVAL DATE 92-10-20 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91584 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E282-12 Provided by IHSNot for Resal

    4、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consistin

    5、g of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

    6、1.2 PIN. The PIN is as shown in the following example: 5962 - 91584 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes

    7、Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devi

    8、ce. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 CY7C332-25 Registered combinatorial 25 ns 02 CY7C332-20 Registered combinatorial 20 ns 1.2.3 Device class designator. The device class designator is a sin

    9、gle letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualifica

    10、tion to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line 1/ Y GDFP2-F28 28 Flat pack 1/ Z GQCC1-J28 28 “J” lead chip carrier 1/ 3 CQCC1-N28 28

    11、Square leadless chip carrier 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Lid shall be transparent to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networki

    12、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc Output volta

    13、ge range applied -0.5 V dc to +7.0 V dc DC input voltage range . -3.0 V dc to +7.0 V dc Maximum power dissipation (PD) . 1.0 W 3/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximum junction temperature (TJ) . +175C Storage temperature ra

    14、nge (TSTG) . -65C to +150C Temperature under bias -55C to +125C Output current into outputs (low) . 12 mA Endurance . 25 erase/write cycles (minimum) 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0.0 V dc Input high vol

    15、tage (VIH) 2.2 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent s

    16、pecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-M-38510 - Microcircuits, General Specification for. MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPAR

    17、TMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these do

    18、cuments are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

    19、maximum levels may degrade performance and affect reliability. 3/ Must withstand the added PD due to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME

    20、COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solici

    21、tation. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201). (Non-Government standards an

    22、d other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the re

    23、ferences cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be i

    24、n accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance wi

    25、th MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and h

    26、erein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. T

    27、he truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, C or D (see 4.3 herein), the devices shall be programmed by the manufacturer pr

    28、ior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Ele

    29、ctrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups spe

    30、cified in table IIA. The electrical tests for each subgroup are described in table I. 3.5 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configuring; two process options are provided for selection in the contr

    31、act, using an altered item drawing. 3.5.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 3.2.3.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programing to verify the specific program configuration. 3.5.2

    32、Manufacturer-programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. Provided by IHSNot for ResaleNo reproduction or networking permitt

    33、ed without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.6 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marke

    34、d. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in a

    35、ccordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.6.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall

    36、be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (se

    37、e 6.7.3 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certifi

    38、cate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.6 herein) to the specified pattern or erased

    39、 (see 4.5 herein). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.10 Notification of

    40、change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.11 Verification and review for device class M. For device class M, DLA Land

    41、 and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.12 Microcircuit group assignment for device cl

    42、ass M. Device class M devices covered by this drawing shall be in microcircuit group number 042 (see MIL-PRF-38535, appendix A). 3.13 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test shall be done only for initial characte

    43、rization and after any design or process changes which may affect the reprogrammability of the device. This test shall consist of 25 program/erase cycles on 25 devices with the following conditions: a. All devices selected for testing shall be programmed in accordance with 3.2.3.1 herein. b. Verify

    44、pattern (see 3.9). c. Erase (see 4.5). d. Verify pattern erasure (see 3.9). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC

    45、FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Output low voltage VOL VCC = 4.5 V, IOL = 8.0 mA, VIN = VIH and VIL 1, 2, 3 All 0.5 V Output high volta

    46、ge VOH VCC = 4.5 V, IOL = -2.0 mA, VIN = VIH and VIL 1, 2, 3 All 2.4 V Input low voltage 1/ VIL 1, 2, 3 All 0.8 V Input high voltage 1/ VIH 1, 2, 3 All 2.2 V Input leakage current IIX VIN = 5.5 to GND, VCC = 5.5 V 1, 2, 3 All -10 +10 A Output leakage current IOZ VCC = 5.5 V VOUT = 5.5 V and GND 1, 2

    47、, 3 All -40 +40 A Output short circuit current 2/ 3/ IOS VCC = 5.5 V, VOUT = 0.5 V 1, 2, 3 All -30 -90 mA Power supply current at frequency 3/ 4/ ICC1 VCC = 5.5 V, IOUT = 0 mA, VIN = GND, f = fMAX 5/ 1, 2, 3 All 200 mA Standby power supply current ICC2 VCC = 5.5 V, IOUT = 0 mA, VIN = GND 1, 2, 3 01

    48、150 mA 02 160 Input capacitance 3/ CIN VCC = 5.0 V, TA = +25C, f = 1 MHz (see 4.4.1e) 4 All 10 pF Output capacitance 3/ COUT VCC = 5.0 V, TA = +25C, f = 1 MHz (see 4.4.1e) 4 All 10 pF Functional tests See 4.4.1c 7, 8A, 8B All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91584 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test


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