1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 03-06-02 Thomas M. Hess B Update boilerplate to current MIL-PRF-38535 requirements. - CFS 08-05-06 Thomas M. Hess REV SHET REV B B B B B B SHEET 15 16 17 18 19 20 REV STATUS REV B B B B B B
2、B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Greg A. Pitz DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Mich
3、ael. A. Frye MICROCIRCUIT, DIGITAL, CMOS, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-01-04 COUNTER/TIMER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89515 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E353-08 Provided by IHSNot for ResaleNo reproducti
4、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, no
5、n-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89515 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). Th
6、e device type(s) identify the circuit function as follows: Device type Generic number Frequency Circuit function 01 Z84C3006 6.17 MHz Counter/timer unit 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Packag
7、e style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VCCsupply voltage range (referenced to ground). -0.3 V dc to +7.0 V dc Voltage on any pin (referenced to ground) . -0.3 V dc to +7.0 V dc St
8、orage temperature range -65C to +150C Maximum power dissipation (PD) per device 1 W Lead temperature (soldering, 10 seconds). +270C Maximum junction temperature (TJ) (at TC= +125C) +180C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage
9、 range +4.5 V dc to +5.5 V dc Minimum high level input voltage (VIH): Logic inputs +2.2 V dc Clock input VCC 0.6 V dc Maximum low level input voltage (VIL): Logic inputs +0.8 V dc Clock input +0.45 V dc Frequency of operation 0 to 6.17 MHz Case operating temperature range (TC) . -55C to +125C Clock
10、rise time 20 ns maximum Clock fall time. 20 ns maximum Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 AP
11、R 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or cont
12、ract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDB
13、OOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Build
14、ing 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemp
15、tion has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) ce
16、rtified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documen
17、ted in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 i
18、s required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein
19、. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
20、,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in ta
21、ble I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL
22、-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on t
23、he device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when
24、the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 and QML38535 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an
25、 approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircui
26、ts delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable req
27、uired documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4
28、3218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Clock input high voltage VIH11, 2, 3 All VCC 0.6 VCC+ 0.3 2
29、/ V Clock input low voltage VIL11, 2, 3 All -0.3 2/ 0.45 V Logic input high voltage VIH21, 2, 3 All 2.2 VCCV Logic input low voltage VIL21, 2, 3 All -0.3 2/ 0.8 V Logic output low voltage VOLIOL= +2.0 mA 1, 2, 3 All 0.4 V Logic output high voltage VOH1IOH= -1.6 mA 1, 2, 3 All 2.4 V Logic output high
30、 voltage VOH2IOH= -250 A 1, 2, 3 All VCC 0.8 V Power supply current ICC1VCC= 5.0 V; CL= 100 pF, VIH= VCC 0.2 V, VIL= 0.2 V, CLK = 6 MHz 1, 2, 3 All 10 mA Power supply current ICC2VCC= 5.0 V; CLK = 0 MHz 1, 2, 3 All 100 A Output leakage current low, open drain outputs ILOLVOUT= 0.4 V 1, 2, 3 All -10
31、+10 A Output leakage current high, open drain outputs ILOHVOUT= 2.4 V 1, 2, 3 All -10 +10 A Darlington drive current 2/ IOHDVOH= 1.5 V, REXT= 1.1 k 1, 2, 3 All -1.5 -5.0 mA Input low current (input and bi- directional) IILVIN= 0.4 V 1, 2, 3 All -10 +10 A Input high current (input and bi- directional
32、) IIHVIN= 2.4 V 1, 2, 3 All -10 +10 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSC
33、C FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max Clock capacitance CCLK4 All 20 pFInput capacitance CIAll 5 pFOutput capacitance COFre
34、quency = 1 MHz TC= +25C See 4.3.1c Unmeasured pins returned to ground 4 All 15 pF Functional tests See 4.3.1d 7, 8 All Maximum frequency 2/ fMAXCL= 100 pF 10% 9, 10, 11 All 6.17 MHz Clock cycle time 2/ 3/ tcyc1See figure 2. See Reference No. 1 4/ CL= 100 pF 10% 9, 10, 11 All 162 ns CLK/TRG cycle tim
35、e (counter mode) tcyc2See figure 2. See Reference No. 21 4/ CL= 100 pF 10% 9, 10, 11 All 2tcyc1ns Clock rise time 2/ trC1See figure 2. See Reference No. 5 4/ CL= 100 pF 10% 9, 10, 11 All 20 ns Clock fall time 2/ tfC1See figure 2. See Reference No. 4 4/ CL= 100 pF 10% 9, 10, 11 All 20 ns CLK/TRG rise
36、 time trC2See figure 2. See Reference No. 22 4/ CL= 100 pF 10% 9, 10, 11 All 40 ns CLK/TRG fall time tfC2See figure 2. See Reference No. 23 4/ CL= 100 pF 10% 9, 10, 11 All 40 ns Clock width high tPWH15/ See figure 2. See Reference No. 2 4/ CL= 100 pF 10% 9, 10, 11 All 65 2/ ns Clock width low tPWL16
37、/ See figure 2. See Reference No. 3 4/ CL= 100 pF 10% 9, 10, 11 All 65 2/ ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO
38、43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max CLK/TRG width high 2/ tPWH27/ See figure 2. Se
39、e Reference No. 25 4/ CL= 100 pF 10% 9, 10, 11 All 120 ns CLK/TRG width low 2/ tPWL28/ See figure 2. See Reference No. 24 4/ CL= 100 pF 10% 9, 10, 11 All 120 ns tSLH1See figure 2. See Reference No. 7 4/ CL= 100 pF 10% 9, 10, 11 All 160 ns CSO, CS1 to clock setup 2/ tSHL1See figure 2. See Reference N
40、o. 7 4/ CL= 100 pF 10% 9, 10, 11 All 160 ns CE to clock setup tSLH2See figure 2. See Reference No. 8 4/ CL= 100 pF 10% 9, 10, 11 All 100 ns IORQ to clock setup tSHL3See figure 2. See Reference No. 9 4/ CL= 100 pF 10% 9, 10, 11 All 70 ns RD to clock setup tSHL4See figure 2. See Reference No. 10 4/ CL
41、= 100 pF 10% 9, 10, 11 All 70 ns tSLH5See figure 2. See Reference No. 13 4/ CL= 100 pF 10% 9, 10, 11 All 40 ns Data in to clock setup tSHL5See figure 2. See Reference No. 13 4/ CL= 100 pF 10% 9, 10, 11 All 50 ns M1 to clock setup tSHL6See figure 2. See Reference No. 14 4/ CL= 100 pF 10% 9, 10, 11 Al
42、l 70 ns CLK/TRG to clock (time for enabling of prescaler on following clock timer mode) tSLH7See figure 2. See Reference No. 27 4/ CL= 100 pF 10% 9, 10, 11 All 150 ns CLK/TRG to clock (setup time for immediate count counter mode) tSLH8See figure 2. See Reference No. 26 4/ CL= 100 pF 10% 9, 10, 11 Al
43、l 150 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. E
44、lectrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit 1/ Min Max tHHL1See figure 2. See Reference No. 6 4/ CL= 100 pF 10% 9, 10, 11 All 0 ns All hold times 2/ tHLH1See figure 2. S
45、ee Reference No. 6 4/ CL= 100 pF 10% 9, 10, 11 All 0 ns tPLH1See figure 2. See Reference No. 11 4/ CL= 100 pF 10% 9, 10, 11 All 130 ns Clock to data out delay tPHL1See figure 2. See Reference No. 11 4/ CL= 100 pF 10% 9, 10, 11 All 200 ns tPLZ1See figure 2. See Reference No. 12 4/ CL= 100 pF 10% 9, 1
46、0, 11 All 110 ns Clock to data out float delay 2/ tPHZ1See figure 2. See Reference No. 12 4/ CL= 100 pF 10% 9, 10, 11 All 110 ns M1 to IEO delay (interrupt immediately preceding M1) 2/ tPHL2See figure 2. See Reference No. 15 4/ CL= 100 pF 10% 9, 10, 11 All 130 ns tPLH3See figure 2. See Reference No.
47、 16 4/ CL= 100 pF 10% 9, 10, 11 All 110 ns IORQ to data out (INTA cycle) tPHL3See figure 2. See Reference No. 16 4/ CL= 100 pF 10% 9, 10, 11 All 160 ns IEI to IEO delay tPHL4See figure 2. See Reference No. 17 4/ CL= 100 pF 10% 9, 10, 11 All 100 ns IEI to IEO delay (after ED decode) tPLH5See figure 2
48、. See Reference No. 18 4/ CL= 100 pF 10% 9, 10, 11 All 110 ns Clock to INT delay (timer mode) tPHL6See figure 2. See Reference No. 19 4/ CL= 100 pF 10% 9, 10, 11 All tcyc1+ 120 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89515 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVI
