1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 04. Editorial changes to pages 2, 3, 5, 6, 7, and 8. Editorial changes throughout. 91-03-22 Michael A. Frye B Add device type 05. Format update, editorial change throughout. 95-10-16 Michael A. Frye C Change in accordance with NOR
2、 5962-R002-97 96-10-04 Ray Monnin D Updated boiler plate for 5 year review lhl 11-07-25 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV D D D SHEET 15 16 17 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/
3、A PREPARED BY Charles Reusing DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael Frye MICROCIRCUIT, ME
4、MORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC CELL ARRAY, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-11-15 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-88638 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E397-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
5、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL
6、-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88638 02 X C Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as fol
7、lows: Device type Generic number Circuit function Toggle speed 02 2018 10 x 10, 1800 gate programmable array 33 MHz 03 2018 10 x 10, 1800 gate programmable array 50 MHz 04 2018 10 x 10, 1800 gate programmable array 70 MHz 05 2018 10 x 10, 1800 gate programmable array 100 MHz 1.2.2 Case outline(s). T
8、he case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-P84 84 pin grid array package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage r
9、ange (VCC) . -0.5 V to 7.0 V Input voltage range (VIN) . -0.5 V to VCC + 0.5 V Voltage applied to three-state output range (VTs) . -0.5 V to VCC + 0.5 V Storage temperature range (TSTG) . -65C to +150C Maximum soldering temperature (soldering, 10 seconds) +260C Thermal resistance (JC) . See MIL-STD-
10、1835 Maximum junction temperature (TJ) +150C 1.4 Recommended operating conditions. Case operating temperature range (TC) -55C to +125C Supply voltage relative to ground range (VCC) 4.5 V dc minimum to 5.5 V dc maximum Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) 0.0 V dc to V
11、CC1/ 84 actual pins used plus one (1) electrically not connected, locator pin = 85; not maximum listed in MIL-STD-1835. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OH
12、IO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those c
13、ited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outli
14、nes. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, B
15、uilding 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific e
16、xemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML
17、) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as doc
18、umented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-385
19、35 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.
20、2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.4 Logic block diagrams. The logic block diagram shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance character
21、istics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. Marking shal
22、l be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of n
23、ot marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-
24、PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7 herein). The certificate of compliance submitted to DLA Land and Mar
25、itime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU
26、IT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing
27、. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers faci
28、lity and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be i
29、n accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, D or E. The test circuit shall be maintained by the man
30、ufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2
31、) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without
32、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A
33、 subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V, IOH= -4.0 mA, VIN= VIHCminimum, VIHTminimum or VILCmaximum, VILTmaximum 1, 2, 3 All 3.7 V Low level output voltage VOLVCC= 5.5 V, IOL= 4.0 mA, VIN= VIHCminimum, VIHTminimum or VILCmaximum, VILTmaximum 1, 2, 3 All 0.4
34、 Quiescent power supply current ICCOVCC= VIN= 5.5 V CMOS 1, 2, 3 All 10 mA TTL 15Power-down supply current ICCPDVCC= VIN= 5.5 V, PWRDWN = 0 V 1, 2, 3 All 0.5 Power-down supply voltage VPDPWRDWN = 0 V see figure 3 1, 2, 3 All 3.5 - V Input leakage current IILVIN= 0 V and 5.5 V, VCC= 5.5 V 1, 2, 3 All
35、 -10 +10 A Output leakage current IOZVIN= 0 V and 5.5 V, VCC= 5.5 V with no lead 1, 2, 3 All -10 +10 High level input voltage TTL VIHT1, 2, 3 All 2 - V Low level input voltage TTL VILT1, 2, 3 All - 0.8 High level input voltage CMOS VIHC1, 2, 3 All 0.7 VCC- Low level input voltage CMOS VILC1, 2, 3 Al
36、l - 0.2 VCCInput capacitance except XTL1 and XTL2 CINSee 4.3.1c 4 All - 10 pF Input capacitance XTL1 and XTL2 CINSee 4.3.1c 4 All 15 Output capacitance COUTSee 4.3.1c 4 All 10 Function test FT See 4.3.1d 7, 8A, 8B All Interconnect + tPID+ tOPS+ 10(tILO) tB1 Measured on 10 columns See figure 3 9, 10,
37、 11 02 238 ns 03 178 04 119 05 86 Interconnect + 10(tITO) + tOPStB29, 10, 11 02 288 03 228 04 159 05 115 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARIT
38、IME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Interconnect + tPID+ tOPS+10(tITO)
39、 + 10(tQLO) tB3Measured on 10 columns See figure 3 9, 10, 11 02 410 ns 03 30204 217 05 172Tested on all CLBs with tICK + interconnect + tCKO+ 2tILOtB4See figure 3 9, 10, 11 02 85 03 6204 4205 33 Tested on all CLBs with tICI+ interconnect + tCIO+ tILOtB59, 10, 11 02 66 03 4904 3805 26.5 Tested on all
40、 CLBs with tICC + interconnect + tCCO+ 2(tILO) tB69, 10, 11 02 90 03 6704 4105 31 Interconnect + tCKO+ tIHCK+ tCKIHtB7Measured on 10 rows. See figure 3. 9, 10, 11 02 318 03 26904 183 05 1283tPID+ interconnect + tPL+ tLI+ 4 (tOPS) tB8Tested on all IOBs See figure 3. 9, 10, 11 02 274 03 14104 32.5 tPL
41、+ tLI+ tOPS+ interconnect tB99, 10, 11 05 32.5 Logic input to output (combinatorial) tILOSee figure 3 1/ 02 20 03 1504 1005 7.5 Logic input to output (transparent-latch) tITO1/ 02 25 03 2004 1405 10 Logic input to output (additional for Q through F) tQLO/ 02 13 03 8 04, 05 6 K clock to output tCKO1/
42、 02 20 03 1504 10.5 05 7 K clock logic-input setup tICK1/ 02 12 03 8 04 7 05 6 K clock logic-input hold tCKI1/ All 2 C clock to output tCCO1/ 02 25 03 1904 1305 9 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD
43、 MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device t
44、ype Limits Unit Min Max C clock logic-input setup tICC1/ 02 12 ns 03 9 04 6 05 5 C clock logic-input hold tCCI1/ 02 6 03, 04 2 05 1 Logic input to G clock to output tCIO1/ 02 37 03 2704 2005 13 Logic input to G clock logic-input setup tICI1/ 02 6 03 4 04 3 05 2 Logic input to G clock logic-input hol
45、d tCII1/ 02 9 03 5 04 4 05 3 Set/reset direct input A or D to out tRIO1/ 02 25 03 2204 1605 10 Set/reset direct through F or G to out tRLO1/ 02 37 03 2804 2105 14 Set/reset direct master reset pin to out tMRQ1/ 02 55 03 4504 4005 17 Set/reset direct separation of set/reset tRS1/ 02 17 03 9 04 7 05 6
46、 Set/reset direct set/reset pulse-width tRPW1/ 02 12 03 9 04 7 05 6 Flip-flop toggle rate Q through F to flip-flop FCLK1/ 02 33 MHz 03 50 04 70 05 100 Clock high tCHSee note 2/ 1/ 02 12 ns 03 8 04 7 05 5 See footnotes at end of able. Provided by IHSNot for ResaleNo reproduction or networking permitt
47、ed without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-88638 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherw
48、ise specified Group A subgroups Device type Limits Unit Min Max Clock low tCLSee note 2/ 1/ 02 12 ns 03 8 04 7 05 5 Pad (package pin) to input direct tPID1/ 02 12 03 8 04 6 05 4 I/O clock to input (storage) tLI1/ 02 20 03 1504 1105 8 I/O clock to pad-input setup tPL1/ 02 12 03 8 04 6 05 4 I/O clock to pad-input setup tPL1/ 02 12 03 8 04 6 05 4 I/O clock to pad-input hold tLP1/ All 0 I/O clock pulse width tLW
