1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil
2、 STANDARD MICROCIRCUIT DRAWING CHECKED BY Laura Leeper THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2M X 36-bit, 1.8 VOLT, 2-WORD AND 4-WORD BURST, RADIATION HARDENED, SYNCHRONOUS STA
3、TIC RANDOM ACCESS MEMORY (SSRAM), MONOLITHIC SILICON DRAWING APPROVAL DATE 12-09-13 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-11202 SHEET 1 OF 30 DSCC FORM 2233 APR 97 5962-E003-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI
4、CROCIRCUIT DRAWING SIZE A 5962-11202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q) and space application (device class V). A
5、choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 F 11202 01 Q X A Federa
6、l RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and ar
7、e marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit funct
8、ion as follows: Maximum Operating Device type Generic number Circuit function Frequency 01 1544AV18-250 2M X 36-bit rad-hard SSRAM 2-word burst 250 MHz 02 1545AV18-250 2M X 36-bit rad-hard SSRAM 4-word burst 250 MHz 1.2.3 Device class designator. The device class designator shall be a single letter
9、identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals P
10、ackage style X See figure 1 165 Ceramic column grid array (CCGA) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-11202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR
11、 97 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) . -0.5 V dc to + 2.9 V dc Supply voltage range to outputs (VDDQ) . -0.5 V dc to VDD2/ Reference supply voltage (VREF) . 0.95 V dc 3/ DC volta
12、ge range on any input . -0.5 V dc to VDD+ 0.3 V dc 4/ DC voltage range on any output pin in High-Z . -0.5 V dc to VDDQ+ 0.3 V dc Current into outputs (Low) . 20 mA Storage temperature range -65C to +150C Case temperature range, (TC) . -55C to +125C Maximum junction temperature (TJ) . 150C 5/ Lead te
13、mperature (soldering, 10 seconds) +260 Thermal resistance, junction-to-case (JC) 8.9 C/W 6/ Maximum power dissipation (PD) . 01 3.23 W 02 2.42 W Maximum operating supply current (VDD+ VDDQ) - IDD. 01 1700 mA 02 1275 mA Maximum operating frequency 01 250 MHz 02 250 MHz 1.4 Recommended operating condi
14、tions. Supply voltage range (VDD) . 1.7 V dc to 1.9 V dc Supply voltage to outputs (VDDQ) . 1.4 V dc to VDD2/ Supply voltage (VSS) 0 V Input high voltage range (VIH) . VREF+ 0.1 V dc to VDDQ+ 0.3 V dc 3/ 4/ Input low voltage range (VIL) . -0.3 V dc to VREF 0.1 V dc 3/ 4/ Case operating temperature r
15、ange (TC) -55C to +125C 5/ 1.5 Radiation features Maximum total dose available (Dose rate = 50-300 rads(Si)/s). 300 Krads(Si) Single event phenomenon (SEP) : No SEL occurs at effective LET(see 4.4.4.4) 120 MeV-cm2/mg 7/ No SEU occurs at on set LET (see 4.4.4.4) 0.13 MeV-cm2/mg 7/ (Single event upset
16、 rate =1.34 x 10-7errors/bit-day ) Dose rate induced upset . 2.0 x 109rad(Si)/sec 7/ Dose rate induced latch-up survivability 1.5 x 1011rad(Si)/sec 7/ Neutron irradiation. 2.0 x 1014n/cm27/ _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation a
17、t the maximum levels may degrade performance and affect reliability. 2/ VDDQ-1.5V (Pulse width less than tCYC/2). 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ Tested initially
18、and after any design or process changes which may affect this parameter. 7/ Typical. Contact the device manufacturer for detailed lot information. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-11202 DLA LAN
19、D AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise spe
20、cified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - I
21、nterface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardizatio
22、n Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited
23、in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM Intern
24、ational, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. JEDEC MO-158 BE-1 - Microelectronic Outlines (Applications for copies should be addressed to JEDEC Solid State Technology Associat
25、ion, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of this document are available from the Institute of Electri
26、cal and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational serv
27、ices.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQU
28、IREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or fu
29、nction as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-11202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 5 DSCC FORM 2234 APR 97 3.2 Design, construction, and phy
30、sical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections sha
31、ll be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Output load circuit. The output load circuit shall be as specified on figure 4. 3.2.5 Block diagram. The block diagram shall be as specified on figure 5. 3.2.6 Timing waveforms. The timi
32、ng waveforms shall be as specified on figure 6. 3.2.7 Radiation test circuit. The radiation test circuit shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.8 Functional tests. Various func
33、tional tests used to test this device are contained in Appendix A (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns shall be under the co
34、ntrol of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the e
35、lectrical performance characteristics and post-irradiation parameter limits are as specified in Table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in Table IIA. The electrical te
36、sts for each subgroup are defined in Table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the op
37、tion of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a
38、“QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted
39、to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for devi
40、ce classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritim
41、e, DLA Land and Maritimes agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 IEEE 1149.1 Serial Boundary Scan (JTAG). The SRAMs descr
42、ibed in this document incorporate a serial boundary scan Test Access Port (TAP). This feature is fully compliant with IEEE Standard 1149.1-2001. The TAP operates using standard 1.8V I/O logic levels. 3.10.1 Disabling the JTAG feature. It is possible to operate the SRAM without using the JTAG feature
43、. To disable the TAP controller, TCK must be tied to LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively connected to VDDthrough a pull-up resistor. TDO must be left unconnected. Upon power up, the device comes up in a rese
44、t state, which does not interfere with the operation of the device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-11202 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234
45、APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions -55 TC +125C 1.7 V VDD 1.9 V 1.4V VDDQ VDD Unless Otherwise Specified 1/ 2/ 3/ Group A Subgroups Device Type Limits Units Min Max Output HIGH Voltage 4/ VOH1 IOH= -0.1 mA, 50 ohm impedance 1, 2, 3 All VDDQ-0.20 VDDQV Out
46、put LOW Voltage 5/ VOL1IOL= 0.1 mA, 50 ohm impedance 1, 2, 3 All VSS 0.20 V Output HIGH Voltage VOH2 IOH= -2.0 mA, 50 ohm impedance 1, 2, 3 All VDDQ/2 - 0.12 VDDQ/2 + 0.12 V Output LOW Voltage VOL2 IOL= 2.0 mA, 50 ohm impedance 1, 2, 3 All VDDQ/2 - 0.12 VDDQ/2 + 0.12 V Input HIGH Voltage 6/ VIH1, 2,
47、 3 All VREF +0.1 VDDQ +0.3 V Input LOW Voltage 6/ VIL1, 2, 3 All -0.3 VREF -0.1 V Input Reference Voltage 6/ 7/ VREF Typical value = 0.75 V 1, 2, 3 All 0.68 0.95 V Input Leakage Current IXGND VI VDDQ1, 2, 3 All -20 20 uA Output Leakage Current IOZGND VI VDDQ,output disabled 1, 2, 3 All -20 20 uA VDD
48、Operating Supply Current IDDVDD= max, IOUT=0 mA f = fMAX = 1/tCYC1, 2, 3 01 1700 mA 02 1275 mA Automatic CE Power-Down Current ISB1VDD = max, both ports deselected, inputs static VIN VIH or VIN VILf = fMAX=1/tCYC1, 2, 3 01 660 mA 02 570 mA Input Capacitance 8/ CIN TA= 25C, f = 1 MHz, VDD = 1.8, VDDQ= 1.5V See 4.4.1e 4 All 10 pF Clock Input Capacitance 8/ CCLK4 All 10 pF Output Capacitance 8/ COUT4 All 10 pF See footnotes at end of table. Provided by IHSNot for
