1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 21 22 23 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 O
2、riginal date of drawing YY-MM-DD CHECKED BY TOM HESS APPROVED BY RAYMOND MONNIN TITLE MICROCIRCUIT, DIGITAL-LINEAR, NINE CHANNEL BUS LVDS TRANSCEIVER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04741 05-03-09 REV PAGE 1 OF 23 AMSC N/A 5962-V027-05 Provided by IHSNot for ResaleNo rep
3、roduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance nine channel bus LVDS transceiver microcirc
4、uit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04
5、741 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 DS92LV090AEP Nine channel bus LVDS transceiver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number
6、of pins JEDEC PUB 95 Package style X 64 MO-136 Plastic gull wing lead chip carrier 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold
7、flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage (VCC) . 4.0 V Enable in
8、put voltage (DE, RE ) -0.3 V to (VCC+ 0.3 V) Driver input voltage (DIN) . -0.3 V to (VCC+ 0.3 V) Receiver output voltage (ROUT) . -0.3 V to (VCC+ 0.3 V) Bus pin voltage (DO / RI) . -0.3 V to 3.9 V Electrostatic discharge (ESD) (HBM 1.5 k, 100 pF) 4.5 kV Driver short circuit duration Momentary Receiv
9、er short circuit duration Momentary Maximum package power dissipation (PD) at 25C : Case X . 1.74 W Derate case X package 13.9 mW/C Thermal resistance, junction to ambient (JA) 71.7C/W Thermal resistance, junction to case (JC) . 10.9C/W Storage temperature range (TSTG) -65C to +150C Lead temperature
10、 (soldering, 4 seconds) . 260C 1.4 Recommended operating conditions. 3/ Supply voltage range (VCC) . 3.0 V minimum to 3.6 V maximum Receiver input voltage 0 V minimum to 2.4 V maximum Maximum input edge rate (20% to 80%) t / V 4/ Data . 1.0 ns/V Control . 3.0 ns/V Operating free-air temperature rang
11、e (TA) . -40C to +85C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is no
12、t implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table I herein provides conditions for actual device operation. 2/ All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to gro
13、und unless otherwise specified except VOD, VOD, and VID. 3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ Generator wa
14、veforms for all tests unless otherwise specified: f = 25 MHz, ZO= 50 , tr, tf+100 mV) H L -100 mV VID +100 mV X H X Z X = High or low logic state L = Low state Z = High impedance state H = High state FIGURE 3. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without
15、 license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 17 FIGURE 4. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZ
16、E A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 18 FIGURE 5. Differential driver DC test circuit. FIGURE 6. Differential driver propagation delay and transition time test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CEN
17、TER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 19 FIGURE 7. Differential driver propagation delay and transition time waveforms. FIGURE 8. Driver three-state delay test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
18、from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 20 FIGURE 9. Driver three-state delay waveforms. FIGURE 10. Receiver propagation delay and transition time test circuit. Provided by IHSNot for ResaleNo reproduction or networking permi
19、tted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 21 FIGURE 11. Receiver propagation delay and transition time waveforms. FIGURE 12. Receiver three-state delay test circuit. Provided by IHSNot for ResaleNo reproduc
20、tion or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 22 FIGURE 13. Receiver three-state delay waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
21、m IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04741 REV PAGE 23 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Suc
22、h procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer
23、s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manuf
24、acturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or cont
25、inued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Package number 2/ Vendor part number 3/ V62/04741-01XA 27014 VEH64A DS92LV090ATVEP 1/ The vendor item drawing establishes an administrative control number for ide
26、ntifying the item on the engineering documentation. 2/ Check with the manufacturer for availability of the following (Enhanced Plastic) versions: DS92LV090TVHXEP. Parts listed with an “X“ are provided in Tape & Reel and parts without an “X“ are in Rails. 3/ For additional ordering and product information, please visit the enhanced plastic web site at CAGE code Source of supply 27014 National Semiconductor 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
