1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dl
2、a.mil/ Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, 16 BIT, 65 MSPS, 1.8 V ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON 13-01-10 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12660 REV PAGE 1 OF 17 AMSC N/A 5962-V001-13
3、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16 bit, 65 million
4、 samples per second (MSPS), 1.8 V analog to digital converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control
5、number for identifying the item on the engineering documentation: V62/12660 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD9266 16 bit, 65 MSPS, 1.8 V analog to digital converter 1.2.2 C
6、ase outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 32 MO-220-WHHD-5 Thin quad chip carrier 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designat
7、or Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 3 1.3 Ab
8、solute maximum ratings. 1/ Analog voltage 1.8 V (AVDD) to analog ground (AGND) -0.3 V to +2.0 V Voltage supply for driver domain (DRVDD) to AGND . -0.3 V to +3.9 V Positive analog input (+VIN), negative analog input (-VIN) to AGND -0.3 V to AVDD+ 0.2 V Clock input (+CLK), clock input (-CLK) to AGND
9、. -0.3 V to AVDD+ 0.2 V Reference voltage (VREF) to AGND . -0.3 V to AVDD+ 0.2 V Reference selection (SENSE) to AGND . -0.3 V to AVDD+ 0.2 V Analog output voltage (VCM) to AGND -0.3 V to AVDD+ 0.2 V Set analog current bias (RBIAS) to AGND . -0.3 V to AVDD+ 0.2 V Serial port interface (SPI) chip sele
10、ct (CSB) to AGND . -0.3 V to DRVDD+ 0.3 V SPI clock input (SCLK) / data format selection (DFS) to AGND . -0.3 V to DRVDD+ 0.3 V SPI data input/output (SDIO) / non-SPI mode power down (PDWN) to AGND -0.3 V to DRVDD+ o.3 V Chip mode select input (MODE) / out of range digital output in SPI mode (OR) to
11、 AGND . -0.3 V to DRVDD+ 0.3 V ADC digital outputs (D1_D0 through D15_D14) to AGND . -0.3 V to DRVDD+ 0.3 V Data clock digital output (DCO) to AGND -0.3 V to DRVDD+ 0.3 V Maximum junction temperature under bias (TJ) . 150C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating cond
12、itions. 2/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Airflow velocity 0 1.0 2.5 m/sec Thermal resistance, junction-to-ambient 3/ 4/ JA37.1 32.4 29.1 C/W Thermal resistance, junction-to-case 3/ 5/ JC3.1 - - C/W Thermal res
13、istance, junction-to-board 3/ 6/ JB20.7 - - C/W Characterization parameter, junction-to-top 3/ 4/ JT0.3 0.5 0.8 C/W 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
14、 or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Use of this product beyond the manufacturers design rules or stated parameters is done at the
15、users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 3/ Per JEDEC JESD51-7 plus JEDEC JESD 51-5 test board. 4/ Per JEDEC JESD51-2 (still air) or JEDEC JESD 51-6 (moving air). 5/ Per MIL-STD-883, method 1021, thermal charac
16、teristics. 6/ Per JEDEC JESD 51-8 (still air). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standar
17、d Outlines for Semiconductor Devices EIA/JEDEC 51-5 - Extension of Thermal Conductivity Test Board Standards for Packages with Direct Thermal Attachment Mechanisms EIA/JEDEC 51-6 - Integrated Circuit Thermal Test Method Environmental Conditions Forced Convection (Moving Air) EIA/JEDEC 51-7 - High Ef
18、fective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JEDEC 51-8 - Integrated Circuits Thermal Test Method Environment Conditions Junction-to-Board (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3
19、834 or online at http:/www.jedec.org) DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia
20、, PA 19111-5094.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit containe
21、r shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, a
22、nd physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 CMOS output data tim
23、ing waveforms. The CMOS output data timing waveforms shall be as shown in figure 3. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 5 TABLE I. Electrical perf
24、ormance characteristics. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max DC specifications. Resolution -55C to +125C 01 16 Bits Accuracy. No missing codes -55C to +125C 01 Guaranteed Offset error -55C to +125C 01 0.30 %FSR Gain error 3/ +25C 01 -1.3 typical %FSR Different
25、ial 4/ nonlinearity error DNL +25C 01 -0.5/+1.0 typical LSB -55C to +125C -0.9/ +1.7 Integral nonlinearity 4/ INL +25C 01 2.6 typical LSB error -55C to +125C 6.5 Offset error temperature drift -55C to +125C 01 2 typical ppm/ C Internal voltage reference. Output voltage 1 V mode -55C to +125C 01 0.98
26、3 1.007 V Load regulation error at 1.0 mA +25C 01 2 typical mV Input referred noise Input referred noise VREF = 1.0 V +25C 01 2.8 typical LSB rms Analog input. Input span, VREF = 1.0 V +25C 01 2 typical VPP Input capacitance 5/ CIN+25C 01 6.5 typical pF Input common mode voltage +25C 01 0.9 typical
27、V Input common mode range -55C to +125C 01 0.5 1.3 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 6 TABLE I. Electrical perf
28、ormance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Reference input resistance -55C to +125C 01 7.5 typical k Power supplies. Supply voltage for ADC core domain AVDD-55C to +125C 01 1.7 1.9 V Supply voltage for output driver domain DRVDD-55C
29、 to +125C 01 1.7 3.6 V Supply current for 4/ ADC core domain IAVDD-55C to +125C 01 62.2 mA Supply current for 4/ for output driver domain IDRVDDAt 1.8 V +25C 01 5.2 typical mA Supply current for 4/ for output driver domain IDRVDDAt 3.3 V +25C 01 9.3 typical mA Power consumption. DC input +25C 01 107
30、 typical mW Sine wave input 4/ DRVDD= 1.8 V -55C to +125C 01 122 mW DRVDD= 3.3 V +25C 132 typical Standby power 6/ +25C 01 44 typical mW Power down power. +25C 01 0.5 typical mW AC specification Signal to noise ratio SNR fIN= 9.7 MHz +25C 01 77.6 typical dBFS fIN= 30.5 MHz +25C 77.4 typical -55C to
31、+125C 76.5 fIN= 70 MHz +25C 76.4 typical Signal to noise and distortion SINAD fIN= 9.7 MHz +25C 01 77.4 typical dBFS fIN= 30.5 MHz +25C 77.2 typical -55C to +125C 76.0 fIN= 70 MHz +25C 76.3 typical See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wi
32、thout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max AC specification continued. Effective number
33、 of bits ENOB fIN= 9.7 MHz +25C 01 12.6 typical Bits fIN= 30.5 MHz +25C 12.5 typical -55C to +125C 12.3 fIN= 70 MHz +25C 12.4 typical Worst second or third harmonic fIN= 9.7 MHz +25C 01 -94 typical dBc fIN= 30.5 MHz +25C -93 typical -55C to +125C -80 fIN= 70 MHz +25C -93 typical Spurious free dynami
34、c range SFDR fIN= 9.7 MHz +25C 01 94 typical dBc fIN= 30.5 MHz +25C 93 typical -55C to +125C 80 fIN= 70 MHz +25C 93 typical Worst other (harmonic or spur) fIN= 9.7 MHz +25C 01 -92 typical dBFS fIN= 30.5 MHz +25C -101 typical -55C to +125C -88 fIN= 70 MHz +25C -98 typical Two tone SFDR fIN= 30.5 MHz
35、(-7 dBFS) +25C 01 90 typical dBc fIN= 32.5 MHz (-7 dBFS) 90 typical Analog input bandwidth +25C 01 700 typical MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT N
36、O. 16236 DWG NO. V62/12660 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Digital specifications. Differential clock inputs (+CLK, -CLK) Logic compliance CMOS / LVDS / LVPECL Internal common mode bias
37、-55C to +125C 01 0.9 typical V Differential input voltage -55C to +125C 01 0.2 3.6 VPPInput voltage range -55C to +125C 01 GND 0.3 AVDD+ 0.2 V High level input current IIL-55C to +125C 01 -10 +10 A Low level input current IIH-55C to +125C 01 -10 +10 A Input resistance RIN-55C to +125C 01 8 12 k Inpu
38、t capacitance CIN+25C 01 4 typical pF Logic inputs (SCLK/DFS, MODE, SDIO/PDWN). 7/ High level input voltage VIH-55C to +125C 01 1.2 DRVDD+ 0.3 V Low level input voltage VIL-55C to +125C 01 0 0.8 V High level input current IIH-55C to +125C 01 -50 -75 A Low level input current IIL-55C to +125C 01 -10
39、+10 A Input resistance RIN-55C to +125C 01 30 typical k Input capacitance CIN-55C to +125C 01 2 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236
40、 DWG NO. V62/12660 REV PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Digital specifications continued. Logic inputs (CSB) 8/ High level input voltage VIH-55C to +125C 01 1.2 DRVDD+ 0.3 V Low level input v
41、oltage VIL-55C to +125C 01 0 0.8 V High level input current IIH-55C to +125C 01 -10 +10 A Low level input current IIL-55C to +125C 01 40 135 A Input resistance RIN-55C to +125C 01 26 typical k Input capacitance CIN-55C to +125C 01 2 typical pF Digital outputs High level output voltage VOHDRVDD= 3.3
42、V, IOH= 50 A -55C to +125C 01 3.29 V DRVDD= 3.3 V, IOH= 0.5 mA 3.25 Low level output voltage VOLDRVDD= 3.3 V, IOL= 1.6 mA -55C to +125C 01 0.2 V DRVDD= 3.3 V, IOL= 50 A 0.05 High level output voltage VOHDRVDD= 1.8 V, IOH= 50 A -55C to +125C 01 1.79 V DRVDD= 1.8 V, IOH= 0.5 mA 1.75 Low level output v
43、oltage VOLDRVDD= 1.8 V, IOL= 1.6 mA -55C to +125C 01 0.2 V DRVDD= 1.8 V, IOL= 50 A 0.05 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12660
44、REV PAGE 10 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Switching specifications. Clock input parameters. Input clock rate -55C to +125C 01 520 MHz Conversion rate 9/ -55C to +125C 01 3 65 MSPS CLK period divi
45、de by 1 mode tCLK-55C to +125C 01 15.38 ns CLK pulse width high tCH+25C 01 7.69 typical ns Aperture delay tA-55C to +125C 01 1.0 typical ns Aperture uncertainty jitter tJ-55C to +125C 01 0.1 typical ps rms Data output parameters Data propagation delay tPD-55C to +125C 01 3 typical ns DCO propagation
46、 delay tDCO-55C to +125C 01 3 typical ns DCO to data skew tSKEW-55C to +125C 01 0.1 typical ns Pipeline delay Latency -55C to +125C 01 9 typical Cycles Wake up time 10/ -55C to +125C 01 350 typical s Standby -55C to +125C 01 300 typical ns Out of range recovery time -55C to +125C 01 2 typical Cycles
47、 Timing specifications. SPI timing requirements. Setup time between the data and the rising edge of SCLK tDS-55C to +125C 01 2 ns Hold time between the data and the rising edge of SCLK tDH-55C to +125C 01 2 ns Period of the SCLK tCLK-55C to +125C 01 40 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND M
