1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Orig
2、inal date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, CMOS, 170 MHz, TRIPLE, 10-BIT HIGH SPEED VIDEO DAC, MONOLITHIC SILICON 12-10-23 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/12637 REV PAGE 1 OF 13 AMSC N/A 5962-V018-13 Provided by IHSN
3、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance CMOS, 170 MHz, triple, 10-bit high
4、 speed video DAC, microcircuit, with an operating temperature range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engin
5、eering documentation: V62/12637 - 01 X B Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADV7123-EP CMOS, 170 MHz, triple, 10-bit high speed video DAC 1.2.2 Case outline(s). The case outlines are as
6、 specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 10 JEDEC MO-220-WKKD Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B
7、Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 3 1.3 Absolute maximum ratings. 1/ 2/ V
8、AAto GND +7.0 V Voltage on any digital pin GND 0.5 V to VAA+ 0.5 V IOUTto GND . 0 V to VAA2/ Ambient operating temperature (TA) -55C to +105C Storage temperature (TS) -65C to 150C Junction temperature (TJ) 150C Lead temperature,( Soldering, 10 sec) 300C Vapor phase Soldering (1 minute) . 220C 2. APP
9、LICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington,
10、VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall
11、 be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3 and table I herein. 3.4 Design, construction, and physical d
12、imension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal f
13、unction shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Timing diagram. The timing diagram shall be as shown in figure 5. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to th
14、e device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ Analog
15、 outputs short circuit to any power supply or common GND can be of an indefinite duration. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 4 TABLE I. Electric
16、al performance characteristics. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max Static performance Resolution (Each DAC) RSET= 680 10 Bits Integral nonlinearity (BSL) -1 +0.5 +1 LSB Differential nonlinearity -1 +0.25 +1 Digital and control inputs Input high voltage VIH2.0 V Input low volta
17、ge VIL0.8 Input current IIN-1 +1 A PSAVEpull up current 20 Input capacitance CIN10 pF Analog outputs Output current Green DAC, SYNC= high 2.0 26.5 mA RGB DAC, SYNC= low 2.0 18.5 DAC to DAC matching 1.0 % Output compliance Range VOC0 1.4 V Output impedance ROUT70 k Output capacitance COUT10 pF Offset
18、 error Tested with DAC output = 0 V 0 0 %FSR Gain error 4/ FSR = 17.62 mA 0 Voltage reference, external Reference range VREF1.12 1.235 1.35 V Voltage reference, internal Reference range VREF1.235 V Power dissipation Digital supply current 5/ fCLK= 50 MHz 2.2 5.0 mA fCLK= 140 MHz 6.5 12.0 fCLK= 517 M
19、Hz 7.5 13.5 Analog supply current RSET= 680 67 72 RSET= 680 8 Standby supply current PSAVE= low, digital and control inputs at VDD2.1 5.0 Power supply rejection ratio 0.1 0.5 %/% See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
20、HS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 6/ Limits Unit Min Typ Max DYNAMIC SPECIFICATIONS AC LINEARITY 3/ Spurious free Dynamic Range to Nyquist 7/
21、 Single ended output fCLK= 50 MHz, fOUT= 1.00 MHz fCLK= 50 MHz, fOUT= 2.51 MHz fCLK= 50 MHz, fOUT= 5.04 MHz fCLK= 50 MHz, fOUT= 20.2 MHz fCLK= 100 MHz, fOUT= 2.51 MHz fCLK= 100 MHz, fOUT= 5.04 MHz fCLK= 100 MHz, fOUT= 20.2 MHz fCLK= 100 MHz, fOUT= 40.4 MHz fCLK= 140 MHz, fOUT= 2.51 MHz fCLK= 140 MHz
22、, fOUT= 5.04 MHz fCLK= 140 MHz, fOUT= 20.2 MHz fCLK= 140 MHz, fOUT= 40.4 MHz 67 67 63 55 62 60 54 48 57 58 52 41 dBc Double ended output fCLK= 50 MHz, fOUT= 1.00 MHz fCLK= 50 MHz, fOUT= 2.51 MHz fCLK= 50 MHz, fOUT= 5.04 MHz fCLK= 50 MHz, fOUT= 20.2 MHz fCLK= 100 MHz, fOUT= 2.51 MHz fCLK= 100 MHz, fO
23、UT= 5.04 MHz fCLK= 100 MHz, fOUT= 20.2 MHz fCLK= 100 MHz, fOUT= 40.4 MHz fCLK= 140 MHz, fOUT= 2.51 MHz fCLK= 140 MHz, fOUT= 5.04 MHz fCLK= 140 MHz, fOUT= 20.2 MHz fCLK= 140 MHz, fOUT= 40.4 MHz 70 70 65 54 67 63 58 52 62 61 55 53 dBc Spurious free Dynamic Range within a window Single ended output fCL
24、K= 50 MHz, fOUT= 1.00 MHz; 1 MHz Span fCLK= 50 MHz, fOUT= 5.04 MHz; 2 MHz Span fCLK= 140 MHz, fOUT= 5.04 MHz; 4 MHz Span 77 73 64 dBc Double ended output fCLK= 50 MHz, fOUT= 1.00 MHz; 1 MHz Span fCLK= 50 MHz, fOUT= 5.04 MHz; 2 MHz Span fCLK= 140 MHz, fOUT= 5.04 MHz; 4 MHz Span 74 73 60 dBc See footn
25、ote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condit
26、ions 6/ Limits Unit Min Typ Max DYNAMIC SPECIFICATIONS Continued. AC LINEARITY Continued. 3/ Total harmonic distortion fCLK= 50 MHz, fOUT= 1.00 MHz TA= 25C -55C TA +105C fCLK= 50 MHz, fOUT= 2.00 MHz fCLK= 100 MHz, fOUT= 2.00 MHz fCLK= 140 MHz, fOUT= 2.00 MHz 66 65 64 64 55 dBc DAC performance Glitsh
27、 impulse DAC to DAC crosstalk 8/ Data feedthrough 9/ 10/ Clock feddthrough 9/ 10/ 10 23 22 33 pV-sec dB dB dB See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 162
28、36 DWG NO. V62/12637 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Unit Min Typ Max TIMING SPECIFICATIONS 3/ 11/ Analog outputs Analog output delay t67.5 ns Analog output Rise/Fall time 12/ t71.0 Analog output transition time 13/ t81
29、5 Analog output skew 14 t91 2 Clock control Clock frequency 15/ fCLK170 MHz Data and control setup t10.68 ns Data and control hold t22.9 Clock period t35.88 Clock pulse width high 14/ t4fCLK_MAX = 170 MHz 2.6 Clock pulse width low 14/ t5fCLK_MAX = 170 MHz 2.6 Pipeline delay 14/ tPD1.0 1.0 1.0 Clock
30、cycles PSAVEup time 14/ t10 4 10 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessari
31、ly be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ VAA= 3.0 V to 3.6 V, VREF= 1.235 V, RSET= 560 , CL= 10 pF, -55C TA +105C , unless otherwise noted; TJ MAX = 110C. 3/ These maximum/minimum specifications are guaranteed b
32、y characterization over the 3.0 V to 3.6 V range. 4/ Gain error = Measured (FSC)/Ideal (FSC) 1) X 100, where ideal (FSC) = VREF/RSETX K X (0x3FFH) and K = 7.9896. 5/ Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V
33、and VDD. 6/ VAA= 3.0 V to 3.6 V, VREF= 1.235 V, RSET= 680 , CL= 10 pF. All specifications are at TA= 25C, unless otherwise noted; TJ MAX = 110C. 7/ This device exhibits high performance when operating with an internal voltage reference, VREF. 8/ DAC to DAC crosstalk measured by holding one DAC high
34、while the other two DAC are making low to high and high to low transactions. 9/ Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 10/ TTL input values are 0 V to 3 V, with input rise/Fall time
35、s of 3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs. 11/ Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL). 12/ Rise time was measured from the 10% and 90% point of zero full scale transition, fall time from 90% to 10%
36、 point of a full scale transition. 13/ Measured from the 50% point of full scale transition to within 2% of the final output value. 14/ Guaranteed by characterization. 15/ fCLKmaximum specification production tested at 125 MHz. Provided by IHSNot for ResaleNo reproduction or networking permitted wit
37、hout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 8 Case X D/EPIN 1IDENTIFIERTOP VIEWASEATINGPLANEA1A2PIN 1IDENTIFIERL1L2D1/E1e b48 PLSBOTTOM VIEW112362548133724Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.70
38、 0.80 D1/E1 3.95 4.25 A1 0.20 REF e 0.50 BSC A2 0.05 L1 0.35 0.45 b 0.18 0.30 L2 0.25 D/E 7.00 BSC NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-220-WKKD. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
39、IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 9 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 G0 25 GND 2 G1 26 GND 3 G2 27 IOB4 G3 28 IOB 5 G4 29 VAA6 G5 30 VAA7 G6 31 IOG8 G7 32 IOG 9 G8 33 IOR10 G9 34 IOG 11
40、BLANK35 COMP 12 SYNC36 VREF 13 VAA37 RSET14 B0 38 PSAVE15 B1 39 R0 16 B2 40 R1 17 B3 41 R2 18 B4 42 R3 19 B5 43 R4 20 B6 44 R5 21 B7 45 R6 22 B8 46 R7 23 B9 47 R8 24 CLOCK 48 R9 FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
41、IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/12637 REV PAGE 10 Case outline X. Terminal Description Number Mnemonic 1 to 10 IN1 Red, Green, and Blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of clock. R0, G0, and B0 are the l
42、east significant data bits. Unused pixel data inputs should be connected to either the regular printed circuit board (PCB) power or ground plate. 14 to 23 D1 39 to 48 S1 11 BLANKComposite Blank Control input (TTL compatible). A logic 0 on this control input drives the analog outputs IOR, IOB, and IO
43、G to the blanking level. The BLANKsignal is latched on the rising edge of CLOCK. When BLANKis a logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored. 12 SYNCComposite Sync Control input (TTL compatible). A logic 0 on the SYNCinput switches off a 40 IRE current source. The sync curr
44、ent is internally connected to the IOG analog output. SYNCdoes not override any other control or data input; therefore, it should only be asserted during the blanking interval. SYNCis latched on the rising edge of CLOCK. If sync information is not required on the green channel, the SYNCinput should
45、be tied to logic 0. 13, 29, 30 VAAAnalog Power supply (3.3 V 10%). All VAApins on this device must be connected. 24 CLOCK Clock Input (TTL compatible). The rising edge of CLOCK latched at the R0 to R9, G0 to G9, B0 to B9. SYNC, and BLANKpixel and control inputs. Typically, the CLOCK input is the pix
46、el clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. 25, 26 GND Ground. The GND pins must be connected. 27, 31, 33 IOB, IOG, IORDifferential Red, Green, and Blue current outputs (High impedance current sources). These RGB video outputs are specified to directly drive
47、RS-343A and RS-170 video levels into a doubly terminated 75 coaxial cable. If the complementary outputs are not required, these outputs should be tie to ground. 28, 32, 34 IOB, IOG, IOR Red, Green and Blue current outputs (High impedance current sources) . These RGB video outputs are specified to specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 coaxial cable. All three currents outputs should have similar output l
