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    DLA DSCC-VID-V62 06616 REV A-2012 MICROCIRCUIT LINEAR DUAL OUTPUT LOW DROPOUT VOLTAGE REGULATOR MONOLITHIC SILICON.pdf

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    DLA DSCC-VID-V62 06616 REV A-2012 MICROCIRCUIT LINEAR DUAL OUTPUT LOW DROPOUT VOLTAGE REGULATOR MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add footnotes 3/ and 4/ to output voltage (reference voltage) test under Table I. Update boilerplate paragraphs to current requirements. - ro 12-08-14 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OH

    2、IO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of

    3、drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCUIT, LINEAR, DUAL OUTPUT, LOW DROPOUT VOLTAGE REGULATOR, MONOLITHIC SILICON 06-03-15 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/06616 REV A PAGE 1 OF 16 AMSC N/A 5962-V073-12 Provided by IHSNot for ResaleNo reproduction or

    4、networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual output, low dropout voltage regulator microcircui

    5、t, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/066

    6、16 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS70345-EP Dual output, low dropout voltage regulator 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter

    7、Number of pins JEDEC PUB 95 Package style X 24 MO-153 Plastic small outline with a thermal pad 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palla

    8、dium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Input voltage range: ( VIN1

    9、) . -0.3 V to +7 V 2/ ( VIN2) . -0.3 V to +7 V 2/ Voltage range at EN -0.3 V to +7 V Output voltage range (VOUT1, VSENSE1) . +5.5 V Output voltage range (VOUT2, VSENSE2) . +5.5 V Maximum RESET , PG1 voltage +7 V Maximum MR1, MR2 , and SEQ voltage VIN1Peak output current Internally limited Operating

    10、virtual junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) -65C to +150C Electrostatic discharge (ESD) rating: Human body model (HBM) . 2 kV 1.4 Recommended operating conditions. 3/ Input voltage range (VIN) . +2.7 V to +6.0 V 4/ Output current (IO) (regulator 1) . 0 to 1

    11、.0 A Output current (IO) (regulator 2) . 0 to 2.0 A Operating virtual junction temperature range (TJ) -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

    12、 or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltages are tied to network ground. 3/ Use of this product beyond the manufacturers desig

    13、n rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 4/ To calculate the minimum input voltage for maximum output current, use the following equation: VI(min)= VO(max)+ VDO(max l

    14、oad). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 Registered a

    15、nd Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the man

    16、ufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 El

    17、ectrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Dia

    18、grams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as show

    19、n in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temp

    20、erature, TJDevice type Limits Unit Min Max Output voltage 3/ 4/ (reference voltage) VO2.7 V 2.5 V then VImax= 6 V, VImin= VO+ 1 V: Line regulation (mV) = ( % / V ) x ( VO( VImax (VO+ 1 V ) / 100 ) x 1000 6/ Input voltage ( VIN1or VIN2) = VO(typ) 100 mV. For the 1.5 V, 1.8 V, and 2.5 V regulators, th

    21、e dropout voltage is limited by input voltage range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DW

    22、G NO. V62/06616 REV A PAGE 9 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 10 Case X Symbol Dimensions Inches Mil

    23、limeters Min Max Min Max A - .047 - 1.20 A1 .001 .005 0.05 0.15 b .007 .011 0.19 0.30 c .005 nominal 0.15 nominal D .303 .311 7.70 7.90 E .169 .177 4.30 4.50 E1 .244 .259 6.20 6.60 e .025 BSC 0.65 BSC L .019 .029 0.50 0.75 n 24 24 Notes: 1. Controlling dimensions are millimeter, inch dimensions are

    24、given for reference only. 2. Body dimensions do not include mold flash or protrusions. Mold flash and protrusion shall not exceed 0.15 mm (0.006 inch) per side. 3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermally enhanced package, m

    25、anufacturer literature number SLMA002 for information regarding recommended board layout. This document is available from the manufacturer. 4. Falls within JEDEC MO-153. FIGURE 1. Case outline Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

    26、,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol 1 GND / HEATSINK 2 VIN13 VIN14 NC 5 MR2 6 MR1 7 EN 8 SEQ 9 GND 10 VIN211 VIN212 GND / HEATSINK 13 GND / HEATSINK 14 VOUT215 VOUT2

    27、16 VSENSE2/ FB2 17 NC 18 RESET 19 PG1 20 NC 21 VSENSE1/ FB1 22 VOUT123 VOUT124 GND / HEATSINK FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 D

    28、WG NO. V62/06616 REV A PAGE 12 Terminal symbol I/O Description EN I Active low enable. GND Regulator ground. GND / HEATSINK Ground / heatsink. MR1 I Manual reset input 1, active low, pulled up internally. MR2 I Manual reset input 2, active low, pulled up internally. NC No connection. PG1 O Open drai

    29、n output, low when VOUT1voltage is less than 95 % of the nominal regulated voltage. RESET O Open drain output, SVS (power on reset) signal, active low. SEQ I Power up sequence control: SEQ = high, VOUT2powers up first; SEQ = low, VOUT1powers up first, SEQ terminal pulled up internally. VIN1I Input v

    30、oltage of regulator 1. VIN2I Input voltage of regulator 2. VOUT1O Output voltage of regulator 1. VOUT2O Output voltage of regulator 2. VSENSE2I Regulator 2 output voltage sense. VSENSE1I Regulator 1 output voltage sense. FIGURE 2. Terminal connections Continued. Provided by IHSNot for ResaleNo repro

    31、duction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 13 NOTES: 1. For most applications, VSENSE1and VSENSE2should be externally connected to VOUTas close as possible to the device. For oth

    32、er implementations, refer to SENSE terminal connection discussion in the application information section. 2. If the SEQ terminal is floating at the input, VOUT2powers up first. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

    33、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 14 NOTES: 1. VRESis the minimum input voltage for a valid RESET . The symbol VRESis not currently listed within EIA or JEDEC standards for semiconductor symbology. 2. VIT - Trip voltage is typical

    34、ly 5% lower than the output voltage (95% VO) VIT-to VIT+is the hysteresis voltage. FIGURE 4. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0661

    35、6 REV A PAGE 15 Notes: 1. VPGis the minimum input voltage for a valid PG. The symbol VPGis not currently listed within EIA or JEDEC standards for semiconductor symbology. 2. VIT-Trip voltage is typically 5% lower than the output voltage (95% VO) VITto VIT+is the hysteresis voltage. FIGURE 4. Timing

    36、waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/06616 REV A PAGE 16 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is re

    37、sponsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELI

    38、VERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6

    39、.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Iden

    40、tification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr

    41、/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Regulator 1 VO(V) Regulator 2 VO(V) Vendor part number V62/06616-01XE 01295 3.3 V 1.2 V TPS70345MPWPREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engine

    42、ering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-


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