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    DLA DSCC-VID-V62 04738 REV A-2011 MICROCIRCUIT DIGITAL OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

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    DLA DSCC-VID-V62 04738 REV A-2011 MICROCIRCUIT DIGITAL OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

    1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-09-16 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE

    2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS, MON

    3、OLITHIC SILICON YY MM DD 04-07-08 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04738 REV A PAGE 1 OF 9 AMSC N/A 5962-V079-11 Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV A PAGE 2 1. SCOPE 1.1

    4、 Scope. This drawing documents the general requirements of a high performance octal bus transceiver with 3-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The

    5、 vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04738 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74AB

    6、T245B-EP Octal bus transceiver with 3-state outputs. 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MO-150 Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead

    7、finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VCC) . -0.5 V to +7.0 V Input voltage range, (VI)(except I/O ports) . -0.5 V t

    8、o +7.0 V 2/ Voltage range applied to any output in the high impedance or power-off stage, (VO) -0.5 V to +5.5 V Current into any output in the low state, (IO) . 96 mA Input clamp current, (IIK) (VI 0) -18 mA Output clamp current, (IOK) (VO 0) . -50 mA Package thermal impedance (JA) 70C/W 3/ Storage

    9、temperature range, (TSTG) -65C to +150C 4/ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operat

    10、ing conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output negative voltage ratings may exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in acco

    11、rdance with JESD 51-7. 4/ Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0473

    12、8 REV A PAGE 3 1.4 Recommended operating conditions. 5/ Supply voltage, (VCC) +4.5 V to +5.5 V Minimum high level input voltage, (VIH) . +2.0 V Maximum low level input voltage, (VIL) +0.8 V Input voltage, (VI) 0.0 V to VCCMaximum high level output current, (IOH) . -24.0 mA Maximum low level output c

    13、urrent, (IOL) +32.0 mA Maximum input transition rise or fall rate, (t/v) 5 ns/V Operating free air temperature, (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documen

    14、ts are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follo

    15、ws: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended oper

    16、ating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be

    17、 as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Function table. The function table shall be as shown in figure 4. 3.5.5 Load circuit and voltage waveforms.

    18、 The load circuit and timing waveforms shall be as specified in figure 5. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV

    19、 A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions unless otherwise specified VCCTA= 25C -55C to +125C Unit Min Max Min Max VIKII= - 18 mA 4.5 V -1.2 -1.2 V High level output voltage VOHIOH= -3 mA 4.5 V 2.5 2.5 V IOH= -3 mA 5.0 V 3 3 IOH= -24 mA 4.5 V 2 2 Low level

    20、output voltage VOLIOL= 32 mA 4.5 V 0.55 0.55 Input current Control inputs IIVI= VCCor GND 0 V to 5.5 V 1 1 A A or B ports 2.1 V to 5.5 V 20 100 High impedance state output current-Power up IOZPUVO= 0.5 V to 2.7 V, OE = X 0 V to 2.1 V 50 50 High impedance state output current-Power down IOZPDVO= 0.5

    21、V to 2.7 V, OE = X 2.1 V to 0 V 50 50 High impedance state output current IOZH2/ VO= 2.7 V, OE 2 V 2.1 V to 5.5 V 10 10 Low impedance state output current IOZL2/ VO= 0.5 V, OE 2 V 2.1 V to 5.5 V -10 -10 Input/output power off leakage current IoffVIor VO 4.5 V 0 V 100 ICEXVO= 5.5 V Outputs high 5.5 V

    22、 50 50 Output current IO3/ VO= 2.5 V 5.5 V -50 -180 -50 -180 mA Quiescent supply current ICCIO = 0, VI= VCCor GND Outputs high 5.5 V 250 250 A Outputs low 5.5 V 30 30 mA Outputs disabled 5.5 V 250 250 A Quiescent supply current delta Data inputs ICCOne input at 3.4 V, other inputs at VCCor GND Outpu

    23、t enabled 5.5 V 1.5 1.5 mA Outputs disabled 5.5 V 50 50 A Control inputs One input at 3.4 V, other inputs at VCCor GND 5.5 V 1.5 1.5 mA Input capacitance Control inputs CiVI= 2.5 V or 0.5 V 5.0 V 4 Typ pF Input/output capacitance A or B ports CiOVO = 2.5 V or 0.5 V 5.0 V 8 Typ See footnote at end of

    24、 the table. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV A PAGE 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 4.5 V VCC 5.5 V unless otherwise specified VCC= 5.0 V, TA= 25C -

    25、55C to +125C Unit Min Max Min Max Propagation delay time, high to low , from input A or B to output B or A tPLHCL= 50 pF 1 3.2 0.8 3.8 ns Propagation delay time, low to high, from input A or B to output B or A tPHL1 3.5 1 4.2 Enable time to high level from input OE to outputs A or B tPZH2 4.5 1.2 6.

    26、2 Enable time to low level from input OE to outputs A or B tPZL1.9 5.3 1.3 6.8 Disable time from high level, from input OE to outputs A or B tPHZ2.2 5.4 2.2 6.1 Disable time from low level, from input OE to outputs A or B tPLZ1.5 4 1.0 4.9 Outputs skew time tsk(o)0.5 1. Testing and other quality con

    27、trol techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product

    28、 performance is assured by characterization and/or design. 2. The parameters IOZHand IOZLinclude the input leakage current. 3. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 4. This is increase in supply current for each input that is

    29、at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV A PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max

    30、 A .078 2.0 E .195 .219 5.00 5.60 A1 .000 0.05 E1 .289 .320 7.40 8.20 b .009 .015 0.22 0.38 e .025 BSC 0.65 BSC c .004 .010 0.09 0.25 L .021 .037 0.55 0.95 D .270 .293 6.90 7.50 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimension

    31、s do not include mold flash or protrusion not to exceed 0.15. 4. Fall within JEDEC MO-150. FIGURE 1. Case outlines. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV A PAGE 7 Pin No. Signal name Pin No. Signal name 1 DI

    32、R 11 B8 2 A1 12 B7 3 A2 13 B6 4 A3 14 B5 5 A4 15 B4 6 A5 16 B3 7 A6 17 B2 8 A7 18 B1 9 A8 19 OE 10 GND 20 VCCFIGURE 2. Terminal connections. FIGURE 3. Logic diagram. Inputs Operation OE DIR L L B data to A bus L H A data to B bus H X Isolation FIGURE 4. Function Table Provided by IHSNot for ResaleNo

    33、 reproduction or networking permitted without license from IHSDEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04738 REV A PAGE 8 Notes: 1. CLincludes probe and test fixture capacitance. 2. Waveform 1 is for an output with internal conditions such that the outpu

    34、t is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. 3. All input pulses are supplied by generators having following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, tf 2.5

    35、 ns. 4. The outputs are measured one at a time with one transition per measurement. 5. All parameters and waveforms are not applicable to all devices. FIGURE 5. Load circuit and voltage waveforms. Provided by IHSNot for Resale-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO.

    36、16236 DWG NO. V62/04738 REV A PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices

    37、, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices.

    38、 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes

    39、 without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing adm

    40、inistrative control number 1/ Device manufacturer CAGE code Vendor part number Top side marking V62/04738-01XE 01295 SN74ABT245BMDBREP ABT245MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for Resale-,-,-


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