1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-02-22 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY
2、Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, OCTAL D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 03-11-14 APPROVED BY Thomas M. Hess SIZE A CO
3、DE IDENT. NO. 16236 DWG NO. V62/04621 REV A PAGE 1 OF 11 AMSC N/A 5962-V031-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 2 1. SCOPE 1.1 Sco
4、pe. This drawing documents the general requirements of a high performance octal D-type transparent latch with 3-state outputs microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification
5、. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04621 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 7
6、4AC373-EP Octal D-type transparent latch with 3-state outputs 1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 JEDEC MS-013 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead f
7、inishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output v
8、oltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp current (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 58C/W 3/ Storage temperature range (TSTG) .
9、-65C to +150C 4/ 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not imp
10、lied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. 4/ Long-t
11、erm high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE
12、IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 3 1.4 Recommended operating conditions. 5/ 6/ Supply voltage range (VCC) . 2.0 V to 6.0 V Minimum high level input voltage (VIH): VCC= 3.0 V 2.1 V VCC= 4.5 V 3.15 V VCC= 5.5 V 3.85 V Maximum low level input voltage (VIL): VCC= 3.0 V 0.9 V VCC= 4.5 V 1.35
13、V VCC= 5.5 V 1.65 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 3.0 V -12 mA VCC= 4.5 V -24 mA VCC= 5.5 V -24 mA Maximum low level output current (IOL): VCC= 3.0 V 12 mA VCC= 4.5 V 24 mA VCC= 5.5 V 24 mA Maximum input t
14、ransition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applicati
15、ons for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ Use of this product beyond the manufacturers
16、design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER,
17、 COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ES
18、DS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as spec
19、ified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be
20、as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IH
21、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limit
22、s Unit Min Max High level output voltage VOHIOH= -50 A 3.0 V 25C, -55C to 125C 01 2.9 V 4.5 V 4.4 5.5 V 5.4 IOH= -12 mA 3.0 V 25C 2.56 -55C to 125C 2.4 IOH= -24 mA 4.5 V 25C 3.86 -55C to 125C 3.7 5.5 V 25C 4.86 -55C to 125C 4.7 Low level output voltage VOLIOL= 50 A 3.0 V 25C, -55C to 125C 01 0.1 V 4
23、.5 V 0.1 5.5 V 0.1 IOL= 12 mA 3.0 V 25C 0.36 -55C to 125C 0.5 IOL= 24 mA 4.5 V 25C 0.36 -55C to 125C 0.5 5.5 V 25C 0.36 -55C to 125C 0.5 Input current IIVI= VCCor GND 5.5 V 25C 01 0.1 A -55C to 125C 1.0 Off-state output current IOZVO= VCCor GND 5.5 V 25C 01 0.25 A -55C to 125C 5.0 Quiescent supply c
24、urrent ICCVI= VCCor GND IO= 0 A 5.5 V 25C 01 4.0 A -55C to 125C 80.0 Input capacitance CIVI= VCCor GND 5.0 V 25C 01 4.5 TYP pF Power dissipation capacitance CpdCL= 50 pF f = 1 MHz 5.0 V 25C 01 40 TYP pF See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitte
25、d without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Pulse duration, LE high tw
26、See figure 5 3.0 V and 3.6 V 25C 01 5.5 ns -55C to 125C 6.5 4.5 V and 5.5 V 25C 4.0 -55C to 125C 5.0 Setup time, data before LE tsuSee figure 5 3.0 V and 3.6 V 25C 01 5.5 ns -55C to 125C 6.5 4.5 V and 5.5 V 25C 4.0 -55C to 125C 5.0 Hold time, data after LE thSee figure 5 3.0 V and 3.6 V 25C 01 1.0 n
27、s -55C to 125C 1.0 4.5 V and 5.5 V 25C 1.0 -55C to 125C 1.0 Propagation delay time, D to Q tPLHSee figure 5 3.0 V and 3.6 V 25C 01 1.5 13.5 ns -55C to 125C 1.0 16.5 4.5 V and 5.5 V 25C 1.5 9.5 -55C to 125C 1.0 11.5 tPHLSee figure 5 3.0 V and 3.6 V 25C 1.5 13.0 -55C to 125C 1.0 16.0 4.5 V and 5.5 V 2
28、5C 1.5 9.5 -55C to 125C 1.0 11.5 See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 7 TABLE I. Electrical performance c
29、haracteristics - Continued. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Propagation delay time, LE to Q tPLHSee figure 5 3.0 V and 3.6 V 25C 01 1.5 13.5 ns -55C to 125C 1.0 16.5 4.5 V and 5.5 V 25C 1.5 9.5 -55C to 125C 1.0 12.0 tPHLSee figure 5 3.0 V and 3.6 V 25C 1.5
30、 12.5 -55C to 125C 1.0 15.0 4.5 V and 5.5 V 25C 1.5 9.5 -55C to 125C 1.0 11.0 Output enable time, OE to Q tPZHSee figure 5 3.0 V and 3.6 V 25C 01 1.5 11.5 ns -55C to 125C 1.0 14.0 4.5 V and 5.5 V 25C 1.5 8.5 -55C to 125C 1.0 10.5 tPZLSee figure 5 3.0 V and 3.6 V 25C 1.5 11.5 -55C to 125C 1.0 13.5 4.
31、5 V and 5.5 V 25C 1.5 8.5 -55C to 125C 1.0 10.0 Output disable time, OE to Q tPHZSee figure 5 3.0 V and 3.6 V 25C 01 1.5 12.5 ns -55C to 125C 1.0 16.0 4.5 V and 5.5 V 25C 1.5 11.0 -55C to 125C 1.0 13.5 tPLZSee figure 5 3.0 V and 3.6 V 25C 1.5 11.5 -55C to 125C 1.0 13.0 4.5 V and 5.5 V 25C 1.5 8.5 -5
32、5C to 125C 1.0 10.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In
33、 the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/0462
34、1 REV A PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 2.65 - 0.104 E 7.39 7.59 0.291 0.299 A1 0.10 0.30 0.004 0.012 E1 10.15 10.65 0.400 0.419 b 0.35 0.51 0.014 0.020 e 1.27 NOM 0.050 NOM c 0.25 NOM 0.010 NOM L 0.40 1.27 0.016 0.050
35、D 12.70 12.95 0.500 0.510 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inches (0.15 mm). 3. Falls within JEDEC MS-013. 4. All linear dimensions are shown in inches (millimeters). Metric equivalents are give
36、n for general information only. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 9 (each latch) Inputs Output OE LE D Q L H
37、 H H L H L L L L X Q0H X X Z FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X Terminal number Terminal symbol Terminal number Terminal symbol 1 OEnullnullnullnull11 LE 2 1Q 12 5Q 3 1D 13 5D 4 2D 14 6D5 2Q 15 6Q 6 3Q 16 7Q 7 3D 17 7D 8 4D 18 8D9 4Q 19 8Q 10 GND 20 VCCFI
38、GURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 10 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is
39、for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the follo
40、wing characteristics: PRR 1 MHz, ZO= 50, tr 2.5 ns, tf 2.5 ns. 4. The outputs are measured one at a time with one input transition per measurement. 5. For 3-state outputs tests: tPLH/tPHLS1 = Open PLZ/tPZLS1 = 2 x VCCtPHZ/tPZHS1 = Open FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot
41、for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04621 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection
42、and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packag
43、ing, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data conta
44、ined herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of
45、 supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side Marking V62/04621-01XE 01295 SN74AC373MDWREP SAC373MEP 1/ The v
46、endor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
