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    DLA DSCC-VID-V62 04615 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS QUADRUPLE 2-INPUT POSITIVE AND GATE MONOLITHIC SILICON.pdf

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    DLA DSCC-VID-V62 04615 REV A-2010 MICROCIRCUIT DIGITAL ADVANCED CMOS QUADRUPLE 2-INPUT POSITIVE AND GATE MONOLITHIC SILICON.pdf

    1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-01-19 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 PMIC N/A PREPARED BY Charles F.

    2、 Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, QUADRUPLE 2-INPUT POSITIVE AND GATE, MONOLITHIC SILICON YY-MM-DD 03-11-03 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO

    3、. V62/04615 REV A PAGE 1 OF 9 AMSC N/A 5962-V026-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents th

    4、e general requirements of a high performance quadruple 2-input positive AND gate microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an admi

    5、nistrative control number for identifying the item on the engineering documentation: V62/04615 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74AC08-EP Quadruple 2-input positive AND gate

    6、1.2.2 Case outlines. The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 14 JEDEC MS-012 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designa

    7、tor Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to VCC+ 0.5 V 2/ Output voltage range (VO) . -0.5 V to VCC+ 0.5 V 2/ Input clamp curren

    8、t (IIK) (VIVCC) 20 mA Output clamp current (IOK) (VOVCC) 20 mA Continuous output current (IO) (VO= 0 to VCC) 50 mA Continuous current through VCCor GND . 200 mA Package thermal impedance (JA) . 86C/W 3/ Storage temperature range (TSTG) . -65C to +150C 1/ Stresses beyond those listed under “absolute

    9、maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended

    10、periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3/ The package thermal impedance is calculated in accordance with JESD 51-7. Provided by IHSNot for ResaleNo reproduction or networking permitted witho

    11、ut license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 3 1.4 Recommended operating conditions. 4/ 5/ Supply voltage range (VCC) . 2.0 V to 6.0 V Minimum high level input voltage (VIH): VCC= 3.0 V 2.1 V VCC= 4.5 V 3.15 V VCC= 5.5

    12、V 3.85 V Maximum low level input voltage (VIL): VCC= 3.0 V 0.9 V VCC= 4.5 V 1.35 V VCC= 5.5 V 1.65 V Input voltage range (VI) . 0.0 V to VCCOutput voltage range (VO) . 0.0 V to VCCMaximum high level output current (IOH): VCC= 3.0 V -12 mA VCC= 4.5 V -24 mA VCC= 5.5 V -24 mA Maximum low level output

    13、current (IOL): VCC= 3.0 V 12 mA VCC= 4.5 V 24 mA VCC= 5.5 V 24 mA Maximum input transition rise or fall rate (t/v) . 8 ns/V Operating free-air temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effec

    14、tive Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and leg

    15、ibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 4/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 5/ Use of this product

    16、 beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,

    17、-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 4 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommend

    18、ed operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall b

    19、e as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The t

    20、iming waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 5 TABLE I. Electrical performance ch

    21、aracteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max High level output voltage VOHIOH= -50 A 3.0 V 25C, -55C to 125C All 2.9 V 4.5 V 4.4 5.5 V 5.4 IOH= -12 mA 3.0 V 25C 2.56 -55C to 125C 2.4 IOH= -24 mA 4.5 V 25C 3.86 -55C to 125C 3.7 5.5 V 25C 4.86 -55C to 125C

    22、 4.7 Low level output voltage VOLIOL= 50 A 3.0 V 25C, -55C to 125C All 0.1 V 4.5 V 0.1 5.5 V 0.1 IOL= 12 mA 3.0 V 25C 0.36 -55C to 125C 0.5 IOL= 24 mA 4.5 V 25C 0.36 -55C to 125C 0.5 5.5 V 25C 0.36 -55C to 125C 0.5 Input current IIVI= VCCor GND 5.5 V 25C All 0.1 A -55C to 125C 1.0 Quiescent supply c

    23、urrent ICCVI= VCCor GND IO= 0 A 5.5 V 25C All 2.0 A -55C to 125C 40.0 Input capacitance CIVI= VCCor GND 25C All 4.5 TYP pF Power dissipation capacitance CPDCL= 50 pF f = 1 MHz 5.0 V 25C All 20 TYP pFPropagation delay time, A or B to Y tPLHSee figure 5 3.0 V and 3.6 V 25C All 1.5 9.5 ns -55C to 125C

    24、1.0 12.5 4.5 V and 5.5 V 25C 1.5 7.5 -55C to 125C 1.0 9.0 tPHLSee figure 5 3.0 V and 3.6 V 25C All 1.5 8.5 ns -55C to 125C 1.0 11.5 4.5 V and 5.5 V 25C 1.5 7.0 -55C to 125C 1.0 8.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance o

    25、ver the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Provided by IHSNot for Resal

    26、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 6 Case X Dimensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max A .069 1.75 E .150 .157

    27、3.81 4.00 A1 .004 .010 0.10 0.25 E1 .228 .244 5.80 6.20 b .014 .020 0.35 0.51 e .050 BSC 1.27 BSC c .008 NOM 0.20 NOM L .016 .044 0.40 1.12 D .337 .344 8.55 8.75 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006

    28、 inches (0.15 mm). 3. Falls within JEDEC MS-012. 4. All linear dimensions are shown in inches (millimeters). Metric equivalents are given for general information only. FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE S

    29、UPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 7 (each gate) Inputs Output Y A B H L X H X L H L L X = Immaterial FIGURE 2. Truth table. FIGURE 3. Logic diagram. Device type 01 Case outlines: X Terminal number Terminal symbol Terminal number Terminal sym

    30、bol 1 1A 8 3Y 2 1B 9 3A 3 1Y 10 3B 4 2A 11 4Y 5 2B 12 4A 6 2Y 13 4B 7 GND 14 VCCFIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/046

    31、15 REV PAGE 8 Notes: 1. CLincludes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50, tr 2.5 ns, tf 2.5 ns. 3. The outputs are measured one at a time with one input transition per measurement. 4. For tPLH/tPHL: S1 = Open

    32、 FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04615 REV PAGE 9 4. VERIFICATION 4.1 Product assurance requirements.

    33、The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5

    34、. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as E

    35、SDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested sou

    36、rce(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-Side M

    37、arking V62/04615-01XE 01295 SN74AC08MDREP SAC08MEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code Source of supply 01295 Texas Instruments, Inc. Semiconductor Group8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-


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