1、Information technology Coding of audio-visual objects Part 3: AudioCAN/CSA-ISO/IEC 14496-3-10(ISO/IEC 14496-3:2009, IDT)National Standard of CanadaNOT FOR RESALE.PUBLICATION NON DESTINE LA REVENTE.Legal Notice for StandardsCanadian Standards Association (CSA) standards are developed through a consen
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18、 conditions of this Legal Notice.Information technology Coding of audio-visual objects Part 3: AudioTechnical Corrigendum 2:2013 (IDT) toNational Standard of CanadaCAN/CSA-ISO/IEC 14496-3-10(ISO/IEC 14496-3:2009, IDT)NOT FOR RESALE. / PUBLICATION NON DESTINE LA REVENTE.Standards Update ServiceTechni
19、cal Corrigendum 2:2013 toCAN/CSA-ISO/IEC 14496-3-10January 2013Title: Information technology Coding of audio-visual objects Part 3: AudioPagination: 6 pagesTo register for e-mail notification about any updates to this publicationgo to shop.csa.caclick on CSA Update ServiceThe List ID that you will n
20、eed to register for updates to this publication is 2420892.If you require assistance, please e-mail techsupportcsagroup.org or call 416-747-2233.Visit CSA Groups policy on privacy at csagroup.org/legal to find out how we protect your personal information.INTERNATIONAL STANDARD ISO/IEC 14496-3:2009TE
21、CHNICAL CORRIGENDUM 2 Published 2011-10-15 INTERNATIONAL ORGANIZATION FOR STANDARDIZATION ORGANISATION INTERNATIONALE DE NORMALISATIONINTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION LECTROTECHNIQUE INTERNATIONALEInformation technology Coding of audio-visual objects Part 3: Audio TECHNICAL CORRI
22、GENDUM 2 Technologies de linformation Codage des objets audio-visuels Partie 3: Codage audio RECTIFICATIF TECHNIQUE 2 Technical Corrigendum 2 to ISO/IEC 14496-3:2009 was prepared by Joint Technical Committee ISO/IEC JTC 1, Information technology, Subcommittee SC 29, Coding of audio, picture, multime
23、dia and hypermedia information. ICS 35.040 Ref. No. ISO/IEC 14496-3:2009/Cor.2:2011(E) ISO/IEC 2011 All rights reserved Technical Corrigendum 2:2013 to CAN/CSA-ISO/IEC 14496-3-10ISO/IEC 14496-3:2009/Cor.2:2011(E) 2 ISO/IEC 2011 All rights reservedReplace Table 11.3 with: Table 11.3 Syntax of block_d
24、ata Syntax No. of bits Mnemonic block_data() block_type; 1 uimsbf if (block_type = 0) const_block; uimsbf js_block; (reserved) 5 if (const_block = 1) if (resolution = 0) / 8 bits const_val; 8 simsbf else if (resolution = 1) / 16 bits const_val; 16 simsbf else if (resolution = 2 | floating = 1) / 24
25、bits const_val; 24 simsbf else / 32 bits const_val; 32 simsbf else js_block; 1 uimsbf if (bgmc_mode = 0) else if (bgmc_mode = 1) 2 uimsbf sub_blocks = 1 0) smp_val0; varies Rice code if (start 1) res1; varies Rice code if (start 2) res2; varies Rice code if (bgmc_mode) for (n = start; n sb_length; n
26、+) msbn; varies BGMC for (k=1; k sub_blocks; k+) for (n = k * sb_length; n (k+1) * sb_length; n+) msbn; varies BGMC for (n = start; n sb_length; n+) if (msbn != tail_code) lsbn; varies uimsbf else tailn; varies Rice code for (k=1; k sub_blocks; k+) for (n = k * sb_length; n (k+1) * sb_length; n+) if
27、 (msbn != tail_code) lsbn; varies uimsbf Technical Corrigendum 2:2013 to CAN/CSA-ISO/IEC 14496-3-10ISO/IEC 14496-3:2009/Cor.2:2011(E) 4 ISO/IEC 2011 All rights reservedSyntax No. of bits Mnemonic else tailn; varies Rice code Else for (n = start; n block_length; n+) resn; varies Rice code if (RLSLMS)
28、 RLSLMS_extension_data() if (!mc_coding | js_switch) byte_align; 07 bslbf Note: random_access_block is true if the current block belongs to a random access frame (frame_id % random_access = 0) and is the first (or only) block of a channel in this frame. If non-adaptive prediction order is used (adap
29、t_order = 0), then in random access frames the block length switching must be constrained so that no blocks in the frame need samples from the previous frame for the prediction process. The condition start = sb_length must be true in all frames. If mc_coding is used, prohibit the use of zero block a
30、nd const block (block_type = 0) as a slave channel, but permit it as a master channel. RLSLMS shall not be used together with block_switching and mc_coding. In 11.4.3 Payloads for Floating-Point Data, replace Note after Table 11.6 Syntax of diff_float_data (changes highlighted): Note: “byte_align” s
31、tands for padding of bits to the next byte boundary. “FlushDict()“ is the function that clears and initializes the dictionary and variables of the Masked-LZ decompression module (see subclause 11.6.9). with: Note: “random_access_block” is defined as (random_access != 0 dec_chars nchars; ) string_cod
32、e; 915 uimsbf Note: “nchars” is the number of characters to be decoded (see 11.6.9). Technical Corrigendum 2:2013 to CAN/CSA-ISO/IEC 14496-3-10ISO/IEC 14496-3:2009/Cor.2:2011(E) ISO/IEC 2011 All rights reserved 5Replace Table 11.14 with: Table 11.14 Elements of diff_float_data Field #Bits Descriptio
33、n / Values use_acf 1 1: acf_flagc is present 0: acf_flagc is not present acf_flagc 1 1: acf_mantissac is present 0: acf_mantissac is not present acf_mantissac 23 Full mantissa data of common multiplier highest_bytec 2 Highest nonzero bytes of mantissa in a frame partA_flagc 1 1: Samples exist in Par
34、t-A 0: No sample exists or all zero in Part-A shift_ampc 1 1: shift_valuec is present 0: shift_valuec is not present shift_valuec 8 Shift value: The shift value is biased by 127. The value (shift_valuec-127) is added to the exponent of all floating-point values of channel c after conversion of decod
35、ed integer to floating-point values, and before addition of integer and the difference data. In 11.6.9.1 Encoder for Floating-Point data, replace following sentences (changes highlighted): If the input signal is 32-bit floating-point, input values are decomposed as shown in 11.14 into three parts: A
36、n estimated common multiplier A, a truncated integer multiplicand sequence Y, and a difference signal Z. The same compression scheme as for normal integer input is applied for the truncated and normalized integer multiplicand sequence. with: If the input signal is 32-bit floating-point, input values
37、 are decomposed as shown in 11.14 into three parts: An estimated common multiplier A, a 24-bit truncated integer multiplicand sequence Y, and a difference signal Z. The same compression scheme as for normal 24-bit integer input is applied for the truncated and normalized integer multiplicand sequenc
38、e. In 11.6.9.3.2.2 Normalization parameters, replace the first sentence of the second paragraph (changes highlighted): First, use_acd is decoded. with: First, use_acf is decoded. In 11.6.9.3.2.5 Masked-LZ decompression, replace the first sentence of the third paragraph (changes highlighted): The ran
39、ge of the code_bits is varied from 9 to 14 bits, since the index of the dictionary is coded as 9 to 15 bits depending on the number of the entries stored in the dictionary. with: The range of code_bits is varied from 9 to 15 bits, since the index of the dictionary is coded as 9 to 15 bits depending
40、on the number of the entries stored in the dictionary. Technical Corrigendum 2:2013 to CAN/CSA-ISO/IEC 14496-3-10ISO/IEC 14496-3:2009/Cor.2:2011(E) 6 ISO/IEC 2011 All rights reservedand the first sentence of the fourth paragraph: The deocder reads (code_bits) bits from bit stream, and gets string_co
41、de. with: The decoder reads (code_bits) bits from bit stream, and gets string_code. Replace 11.6.9.3.3.3 Multiplication of the common multiplier with: After conversion, the common multiplier A is reconstructed from acf_mantissac and multiplied to Fcn, and the result is set to Fcn. The computing proc
42、edure of multiplication is as follows. Step 1: Sign bit setting: The sign of the result is the same as that of Fcn. Step 2: Multiplication of mantissa: (acf_mantissac | 0x0800000) is multiplied to (mantissa bits of Fcn | 0x0800000) in a 64-bit integer resister. Step 3: Normalization: The result of 6
43、4-bit integer multiplication is normalized to 24-bit precision, and represented with 23 bits after discarding the top bit. Since 1.0 = (acf_mantissac | 0x0800000)*2-23, (mantissa part of Fcn | 0x0800000) *2-23 2.0, the result of the multiplication is in the range 1, 4). Consequently, it might be nec
44、essary to normalize by repeatedly shifting one bit to the right and incrementing the exponent. Step 4: Rounding; The rounding mode “round to nearest, to even when tie“ is applied to round off the normalized mantissa of the result. Normalization process might be needed after the rounding. Replace 11.
45、6.9.3.3.4 Addition of difference value of mantissa with: After the multiplication, the reconstructed difference value of the mantissa Dcn is added to the floating-point data Fcn, and the result is set to Fcn. The computing procedure of addition is as follows. Step 1: Addition of mantissa: (Dcn) is a
46、dded to (mantissa bits of Fcn | 0x0800000) in a 32-bit integer resister. Step 2: Normalization: The result of 32-bit integer addition is normalized to 24-bit precision, and represented with 23 bits after discarding the top bit. Since (Dcn)*2-23 1.0, and 1.0 = (mantissa part of Fcn | 0x0800000) *2-23
47、 2.0, the result of the multiplication is in the range 1, 3). Consequently, it might be necessary to normalize by repeatedly shifting one bit to the right and incrementing the exponent. Step 4: Truncation: The rounding is not needed for this addition because whenever shifting occurs, the LSB of the
48、resulting mantissa equals 0. Technical Corrigendum 2:2013 to CAN/CSA-ISO/IEC 14496-3-10Copyright NoticeThis Amendment to the International Standard contains information copyright protected by the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). Except as permitted under the laws of Canada, no extract of this Amendment to the International Standard may be reproduced,
