1、BRITISH STANDARD BS EN 190116:1994 Harmonized system of quality assessment for electronic components Family specification: AC MOS digital integrated circuits The European Standard EN190116:1993 has the status of a British StandardBSEN190116:1994 This British Standard, having been prepared under the
2、directionof the Electronic Components Standards PolicyCommittee, was publishedunder the authorityofthe Standards Boardand comes into effect on 15March1994 BSI 01-2000 The following BSI references relate to the work on this standard: Committee reference ECL/24 Draft for comment 92/27856 DC ISBN 0 580
3、 22598 4 Cooperating organizations The European Committee for Electrotechnical Standardization (CENELEC), under whose supervision this European Standard was prepared, comprises the national committees of the following countries: Austria Italy Belgium Luxembourg Denmark Netherlands Finland Norway Fra
4、nce Portugal Germany Spain Greece Sweden Iceland Switzerland Ireland United Kingdom Amendments issued since publication Amd. No. Date CommentsBSEN190116:1994 BSI 01-2000 i Contents Page Cooperating organizations Inside front cover National foreword ii Foreword 2 1 Limiting conditions of use for the
5、family 5 2 Recommended operating and associated characteristics for the family 5 3 Test methods and procedures mechanical data 15 4 Inspection requirements 27 National annex NA (informative) Committees responsible Inside back cover National annex NB (informative) Cross-references Inside back cover F
6、igure 1 Loading circuit 11 Figure 2 Transition times and propagation delay times 11 Figure 3 Clock-pulse rise and fall times and pulse width 11 Figure 4 Set-up times, hold times, removal time and propagation delay times for edge triggered sequential logic circuits 12 Figure 5 Loading circuit 12 Figu
7、re 6 3-state propagation delay wave shapes 13 Figure 7 Loading circuit 13 Figure 8 Transition times and propagation delay times 13 Figure 9 Clock-pulse rise and fall times and pulse width 14 Figure 10 Set-up times, hold times, removal time and propagation delay times for edge triggered sequential lo
8、gic circuits 14 Figure 11 Loading circuit 14 Figure 12 3-state propagation delay wave shapes 15 Figure 13 16 Figure 14 Input pulse waveforms 18 Figure 15 Example of a test set-up for positive and negative trigger current 20 Figure 16 Timing for latch-up immunity tests 21 Figure 17 22 Figure 18 14-le
9、ad pinout for20-terminal lead-less chip carrier 24 Figure 19 16-lead pinout for20-terminal lead-less chip carrier 24 Figure 20 18-lead pinout for20-terminal lead-less chip carrier 25 Figure 21 24-lead pinout for28-terminal lead-less chip carrier 25 Table 1 AC series 6 Table 2 ACT series 8 Table 3 15
10、 Table 4 23 Table 5 27BSEN190116:1994 ii BSI 01-2000 National foreword This British Standard has been prepared under the direction of the Electronic Components Standards Policy Committee and is the English language version of EN190116:1993 Family specification: AC MOS digital integrated circuits, pu
11、blished by the European Committee for Electrotechnical Standardization (CENELEC) Electronic Components Committee (CECC). The British Standard which implements the CECC Rules of Procedure is BS9000 General requirements for a system for electronic components of assessed quality Part2:1991 Specificatio
12、n for the national implementation of the CECC system. A British Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal
13、obligations. Summary of pages This document comprises a front cover, an inside front cover, pages i and ii, theEN title page, pages2 to30, an inside back cover and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in th
14、e amendment table on the inside front cover.EUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN190116 August 1993 UDC Descriptors: Quality, electronic components, AC MOS digital integrated circuits English version Family specification: AC MOS digital integrated circuits Spcification de famille: Cir
15、cuits intgrs logiques AC MOS Familienspezifikation This European Standard was approved by CENELEC Electronic Components Committee (CECC) on06 December1992. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard t
16、he status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the General Secretariat of the CECC or to any CENELEC member. This European Standard exists in three official versions (Englis
17、h, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the CECC General Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austri
18、a, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and UnitedKingdom. The membership of the CECC is identical, with the exception of the national electrotechnical committees of Greece, Iceland and Luxe
19、mbourg. CECC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B-1050 Brussels 1993 Copyright reserved to CENELEC members Ref. No. EN190116:1993 EEN190116:1
20、993 BSI 01-2000 2 Foreword The CENELEC Electronic Components Committee (CECC) is composed of those member countries of the European Committee for Electrotechnical Standardization (CENELEC) who wish to take part in a harmonized System for electronic components of assessed quality. The object of the S
21、ystem is to facilitate international trade by the harmonization of the specifications and quality assessment procedures for electronic components, and by the grant of an internationally recognized Mark, or Certificate, of Conformity. The components produced under the System are thereby acceptable in
22、 all member countries without further testing. This European Standard was prepared by CECC WG9, “Integrated circuits”. The text of the draft based on document CECC (Secretariat)3120 was submitted to the formal vote; together with the voting report, circulated as document CECC (Secretariat)3275 it wa
23、s approved by CECC as EN190116 on06 December1992. The following dates were fixed: latest date of announcement of the EN atnational level (doa)1994-01-11 latest date of publication ofan identical national standard (dop)1994-07-11 latest date of declaration ofnational standards obsolescence 1994-07-11
24、 latest date of withdrawal of conflicting national standards (dow)2004-01-11EN190116:1993 BSI 01-2000 34 blankEN190116:1993 BSI 01-2000 5 1 Limiting conditions of use for the family (Not for inspection purposes) 1.1 Maximum supply voltage positive V DD=+6 V 1.2 Maximum supply voltage negative V CC=0
25、,5 V 1.3.1 Maximum dc input protection diode current 1.3.2 Maximum input voltage V I= V DD +0,5V 1) 1.4.1 Maximum dc output diode current 1.4.2 Maximum output voltage V O= V DD +0,5V 1) 1.5 Maximum dc output source or sink current per output pin I O= 50mA 1.6 Maximum dc, supply I DDor I SSpin curren
26、t I DDor I GND= 100mA (For up to four outputs per device add 25mA for each additional output). 1.7 Ambient operating temperature range T amb 74 AC/ACT:0 C to+70 C 54 AC/ACT: 55 C to+125 C 1.8 Storage temperature range T stg 65 C to+150 C 2 Recommended operating and associated characteristics for the
27、 family (Notforinspection purposes) These conditions apply over the operating temperature range, unless otherwise specified in the DS. All voltages are referenced to ground. AC SERIES: Operating supply voltages V DDB=3 V(*) to V DDA=5,5 V * No parametric or switching characteristics are specified at
28、 V DDless than3V. At V DDbetween2V and3V the output conditions will stay at their previous state so battery back-up is allowed for data retention at these voltages, with the following conditions: V IH U 0,7 V DD ; V IL k 0,3 V DD ; V OH U 0,7 V DD(I OH=20 A) and V OL k 0,3V DD (I OL=+20A) I IK= 20m
29、A OR (whichever is the worst case) 1) Unless otherwise specified in the detail specification. I OK= 50mA OR (whichever is the worst case)EN190116:1993 6 BSI 01-2000 Table 1 AC series Parameters Symbol V DD (V) 54/74 AC Unit T ambmin. +25 C T ambmax. min. max. min. max. min. max. CONDITIONS OF TEST 2
30、.1 High level input voltage V IHB 3,0 2,1 2,1 2,1 V 4,5 3,15 3,15 3,15 V 5,5 3,85 3,85 3,85 V 2.2 Low level input voltage V ILA 3,0 0,9 0,9 0,9 V 4,5 1,35 1,35 1,35 V 5,5 1,65 1,65 1,65 V DC PARAMETERS TO BE VERIFIED IN SUB-GROUP A3, A4a, A4b 2.3 Quiescent supply current I DDA 5,5 8,0 8,0 80,0 A V I
31、= 0V or V DD a I O=0A 2.4 High level output voltage V OHB V I= V IHBor V ILA b 2.4.1 I O=50A 3,0 4,5 5,5 2,9 4,4 5,4 2,9 4,4 5,4 2,9 4,4 5,4 V V V 2.4.2 I O=12mA 3,0 2,4 2,56 2,4 V 2.4.3 I O=24mA 4,5 5,5 3,7 4,7 3,86 4,86 3,7 4,7 V V 2.5 Low level output voltage V OLA V I= V IHBor V ILA b 2.5.1 I O=
32、+50A 3,0 4,5 5,5 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 V V V 2.5.2 I O=+12mA 3,0 0,4 0,36 0,50 V 2.5.3 I O=+24mA 4,5 5,5 0,4 0,4 0,36 0,36 0,50 0,50 V V 2.6 Positive a) and negative b) input clamping voltage |V IK | 0,4 1,5 V a) GND open, V DD =0 V b) V DDopen, GND =0 V |I IK | =1mA 2.7 Input leakage
33、current |I I(off)A | 5,5 0,1 0,1 1,0 A V I=0V or V DD a Unless otherwise specified in the DS b Not applicable to open drain outputsEN190116:1993 BSI 01-2000 7 Table 1 AC series Parameters Symbol V DD (V) 54/74 AC Unit T ambmin. +25 C T ambmax. min. max. min. max. min. max. 2.8 3-state output off-sta
34、te current |I OZA | 5,5 0,5 0,5 10,0 A V I= V DDor0 V V O=0 V for I OZL V O= V DDfor I OZH CAPACITANCE TO BE VERIFIED IN SUB-GROUP D5 2.9 Power dissipation capacitance C PDA a 5,5 a pF ADDITIONAL INFORMATION (Not for inspection purpose) 2.10 Noise margin at low level output (V ILA V OLA ) V NLB 3,0
35、4,5 5,5 0,8 1,25 1,55 0,8 1,25 1,55 0,8 1,25 1,55 V V V I O=+50A 2.11 Noise margin at high leveloutput (V OHB V IHB ) V NHB 3,0 4,5 5,5 0,8 1,25 1,55 0,8 1,25 1,55 0,8 1,25 1,55 V V V I O=50A 2.12 Input rise and fall time between V ILAand V IHB t r , t f 3,6 to 5,5 8,0 8,0 8,0 ns/V b 2.13 Maximum co
36、ntinuous internal power dissipation with reference to derating curve or factor related to reference point temperature or ambient temperature P DA T jA=150 C Reduction factor (mW/ C) Case DG: P DA=1,25 W f =10mW/ C Case PC: P DA=1,25 W f =11mW/ C a See measurement method in clause3.4 here after and l
37、imits for each type in the relevant DS. b Except for Schmitt inputs.EN190116:1993 8 BSI 01-2000 Table 2 ACT series Operating supply voltages V DDB=4,5V to V DDA=5,5 V Parameters Symbol V DD (V) 54/74 ACT Unit T ambmin. +25 C T ambmax. min. max. min. max. min. max. CONDITIONS OF TEST 2.1 High level i
38、nput voltage V IHB 4,5 5,5 2,0 2,0 2,0 2,0 2,0 2,0 V V 2.2 Low level input voltage V ILA 4,5 5,5 0,8 0,8 0,8 0,8 0,8 0,8 V V DC PARAMETERS TO BE VERIFIED IN SUB-GROUP A3, A4a, A4b 2.3 Quiescent supply current I DDA 5,5 8,0 8,0 80,0 A 2.3.1 V I=0V or V DD a I O=0A 2.3.2 Additional worst case supply c
39、urrent per input %I DDT 5,5 1,6 1,6 1,6 mA I O=0A One input at: V I= V DD 2,1 V others at: V I=0V or V DD 2.4 High level output voltage V OHB V I= V IHBor V ILA b 2.4.1 I O=50A 4,5 5,5 4,4 5,4 4,4 5,4 4,4 5,4 V V 2.4.2 I O=24mA 4,5 5,5 3,7 4,7 3,86 4,86 3,7 4,7 V V 2.5 Low level output voltage V OLA
40、 V I= V IHBor V ILA b 2.5.1 I O=+50A 4,5 5,5 0,1 0,1 0,1 0,1 0,1 0,1 V V 2.5.2 I O=+24mA 4,5 5,5 0,4 0,4 0,36 0,36 0,5 0,5 V V 2.6 Positive a) and negative b) input clamping voltage |V IK | 0,4 1,5 V a) GND open, V DD=0 V b) V DDopen, GND =0 V |I IK | =1mA a Unless otherwise specified in the DS b No
41、t applicable to open drain outputs.EN190116:1993 BSI 01-2000 9 Table 2 ACT series 2.14 Functional test conditions for Sub-Group A2 Input levels1 or0 are applied to each test of the functional verification sequence, and the corresponding output levels1 or0 are successively verified. Parameters Symbol
42、 V DD (V) 54/74 ACT Unit T ambmin. +25 C T ambmax. min. max. min. max. min. max. 2.7 Input leakage current |I I(off)A | 5,5 0,1 0,1 1,0 A V I=0V or V DD 2.8 3-state output off-state current |I OZA | 5,5 0,5 0,5 10,0 A V I= V DDor0 V V O=0V for I OZL V O= V DDfor I OZH CAPACITANCE TO BE VERIFIED IN S
43、UB-GROUP D5 2.9 Dissipation power capacitance C PDA 5,5 a pF a ADDITIONAL INFORMATION (not for inspection purpose) 2.10 Noise margin at low level output (V ILA V OLA ) V NLB 4,5 5,5 0,7 0,7 0,7 0,7 0,7 0,7 V V I O=+50A 2.11 Noise margin at high level output (V OHB V IHB ) V NHB 4,5 5,5 2,4 3,4 2,4 3
44、,4 2,4 3,4 V V I O=50 A 2.12 Input rise and fall time between V ILAand V IHB t r , t f 4,5 5,5 10,0 10,0 10,0 10,0 10,0 10,0 ns/V ns/V b 2.13 Maximum continuous internal power dissipation with reference to rating curve or factor related to reference point temperature or ambient temperature P DA T jA
45、=+150 C Reduction factor (mW/ C) Case DG = P DA=1,25 W f =10mW/ C Case PC = P DA=1,25 W f =11mW/ C a See measurement method in clause3.4 here after and limits for each type in the relevant DS. b Except for Schmitt inputs.EN190116:1993 10 BSI 01-2000 2.14.1 54/74 AC Series 2.14.2 54/74 ACT Series 2.1
46、5 Dynamic characteristics(54/74 AC,54/74 ACT series) 2.15.1 Pulse generator and driving circuit The following conditions shall be met: Output impedance of pulse generator:507 10%; Impedance of the driving circuit cable from the generator, including the test equipment:507 10%; Low level input voltage
47、:0V 0,1V; High level input voltage: V DD 0,1V (AC series);3V 0,1V (ACT series); Rise time of the input signal: t r k 5 ns (measured from10% to90% of the step amplitude); Fall time of the input signal: t f k 5 ns (measured from90% to10% of the step amplitude); Pulse repetition frequency:k 5MHz. I OH=
48、1mA; I OL=1mA V DD=3,0V Inputs 1 =2,5 V 0 =0,5 V Outputs 02,4 V V DD=4,5V Inputs 1 = 3,7 V 0 = 0,8 V Outputs 03,6 V V DD= 5,5V Inputs 1 = 4,5 V 0 = 1,0 V Outputs 04,4 V I OH=1mA; I OL=1mA V DD= 4,5V Inputs 1 = 2,4 V 0 = 0,4 V Outputs 03,6 V V DD= 5,5V Inputs 1 = 2,4 V 0 = 0,4 V Outputs 04,4 VEN19011
49、6:1993 BSI 01-2000 11 2.15.2 Switching waveforms and loading circuits 1) Switching waveforms for54/74 AC Standard or bus driver outputs Outputs should be switching from10% V DDto90% V DDin accordance with device truth table. For f max.duty cycle =50%.t r =t fshall be as fast as required such they do not limit the f max.or minimum pulse width measurement. Figure 1 Loading circuit Figure 2 Transition times
