1、AD/DA (v.5b),1,CENG4480_A3 Analog/Digital Conversions,Analog to Digital (AD), Digital to Analog (DA) conversion,AD/DA (v.5b),2,Analog/digital conversions,Topics Digital to analog conversion Analog to digital conversion Sampling-speed limitation Frequency aliasing Practical ADCs of different speed,AD
2、/DA (v.5b),3,Digital to Analogue Conversion,DAC,AD/DA (v.5b),4,NMAX (bit length) DAC,Input code n (NMAX bit Binary code) 0110001 0100010 0100100 0101011 : :,Output voltage = Vout(n),V+ref ( High Reference Voltage),V-ref (Low Reference Voltage),Digital to analog converter (DAC),AD/DA (v.5b),5,DAC: ba
3、sic equation,At n=0, Vout(0) = V-refAt max. n_max= 2NMAX -1, (E.g. NMAX=8, n_max=28-1=255) Vout cannot reach V+ref , E.g. NMAX=8, n=0, 1, 2, 255. Some DACs have internal reference voltage settings, some can be set externally.,Code (n),Exercise 3.1,Answer the questions for a 10-bit DAC. How many digi
4、tized level can you use? If V+ref=10V, V-ref=0V, calculate the code to make the output to be around 3 Volts. What is the maximum voltage you can obtain?,AD/DA (v.5b),6,Student ID: _ Name: _ Date:_ (Submit this to the tutor at the end of the lecture.),AD/DA (v.5b),7,DAC: characteristics,Glitch: A tra
5、nsient spike in the output of a DAC that occurs when more than one bit changes in the input code. Use a low pass filter to reduce the glitch Use sample and hold circuit to reduce the glitch Settling time: Time for the output to settle to typically 1/4 LSB after a change in DA output.,AD/DA (v.5b),8,
6、Two DAC implementations,Type 1: Weighted Adder DAC Easy to design, use many different Resistor values so it is difficult to manufacture. Type 2: R-2R Resistive-Ladder DAC Use only two R and 2R resistor values, easy to manufacture.,AD/DA (v.5b),9,Type 1: Weighted Adder DAC (E.g. N=8),Virtual earth V-
7、ref,i=8, 28-8 R = Ri=7, 28-7 R = 2R : :i=3, 28-3 R = 25R i=2, 28-2 R = 26Ri=1, 28-1 R = 27R,Resistor=2(N-i)*R,Ii=8 =28-1 *I1=27 * I1,I=Ii=1=Current= (Vref -V-ref)/(28-1R)=(1/28-1)(Vref -V-ref)/R,Ii=1,Ii=8,Resistor,AD/DA (v.5b),10,When ith bit (e.g. N=8, i=7 , N-i=1) = 1 ith analog switch (FET transi
8、stor) is turned on Ii then flows thru. Resistor 2N-iR,Weighted Adder DAC (Contd),AD/DA (v.5b),11,When n has only one bit turned-on,input side,feedback side,Weighted Adder DAC (Contd),AD/DA (v.5b),12,E.g. a 4-bit DAC, N=4. Input code=0101=n=n3+n1 (two bits are on)=binary0100+binary0001,When n has mul
9、tiple on-bits,Weighted Adder DAC (Contd),* difficult to make because it require a wide range of different precise resistors Rs,bit3 is on,bit1 is on,bit1,bit3,Exercise 3.2,For Weighted Adder DAC, V+ref=10V, V-ref=0V , R=1K calculate the current I and V0 when the input is I V0 Bit7,Bit0 0000 0000=_ 0
10、000 0001=_ 1010 1010=_ 1111 1111=_,AD/DA (v.5b),13,AD/DA (v.5b),14,Practical resistor network DAC and audio amplifier (not perfect but ok) Set R=2K,Because ideal resistors are difficult to find in the market,AD/DA (v.5b),15,Type 2: R-2R Resistive-Ladder DAC,Vertical current,AD/DA (v.5b),16,Required
11、only R the other goes to the op-amp negative-feedback point Where Since inputs V+ V- of the opamp inputs are the same , the vertical current will not be changed by input code n,DAC type2: R-2-R resistor-ladder,Exercise 3.3,For R-2-R resistor-ladder DAC, V+ref=10V, V-ref=0V , R=1K calculate the curre
12、nt I1 and V0 when the input is I1 V0 Bit7,Bit0 0000 0000=_0 0_ 0000 0001=_ 1010 1010=_ 1111 1111=_,AD/DA (v.5b),17,AD/DA (v.5b),18,Analog to Digital Conversion,ADC,AD/DA (v.5b),19,Analog to Digital Conversion ADC,N (MAX) bit ADC,output code = n 0110001 0100010 0100100 0101011 : : :,Input voltage = V
13、),V+ref,V-ref,AD/DA (v.5b),20,ADC Major characteristics,n=converted code, V=input voltage, The linearity measures how well the transition voltages lie on a straight line. The differential linearity measures the equality of the step size. Conversion time:between start convert and result generated Con
14、version rate=inverse of conversion time,AD/DA (v.5b),21,Analog to digital converter example,Convert an analog level to digital output From 1, e.g. V-ref=0V, V=10mV.,AD/DA (v.5b),22,ADC Type 1: Integrating or dual slope,Accumulate the input current on a capacitor for a fixed time and then measure the
15、 time (T) to discharge the capacitor at a fixed discharge rate. 1) S1-V1:Integrate the input on the cap. For N clock ticks 2) S1- -Vref: restart clock (S2-counter) discharge C at know rate(governed by -Vref and R) 3) When the cap. is discharged to 0 voltage, the comparator will stop the counter.,pro
16、blem -very slow,AD/DA (v.5b),23,Integrating dual slope ADC: Simplified Diagram,Discharge time for stopping counter by S2 depends on RC and Q,AD/DA (v.5b),24,Type 2: Tracking ADC,The ADC repeatedly compares its input with DAC outputs. Up/down count depends on input/DAC output comparison.,Main problem
17、 also slow,AD/DA (v.5b),25,Type 3 ADC : successive approximation,Faster, use binary search to determine the output bits.,problem still slow although faster than types 1 & 2,AD/DA (v.5b),26,Flow chart of Successive-approximation ADC,Exercise 3.4 Successive-approximation ADC,How many times it goes thr
18、ough inner loop (analog input DA output is yes) if the output is expected to be the following? Bit7,Bit0 0000 0000=_ 0000 0001=_ 1010 1010=_ 1111 1111=_,AD/DA (v.5b),27,AD/DA (v.5b),28,Type 4 ADC : Flash ADC (very fast),Divide the voltage range into 2N-1 levels; use 2N-1 comparators to determine wha
19、t the voltage level is Use a 2N-1 input to N bit priority decoder to work out the binary number,AD/DA (v.5b),29,Diagram of a flash ADC 1,AD/DA (v.5b),30,Type 4 ADC : Flash ADC (contd),Very fast for high quality audio and video. Very expensive for wide bits conversion. Sample and hold circuit usually
20、 NOT required. The number of comparators needed is 2N-1 which grows rapidly with the number of bits E.g. for 4-bit, 15 comparators; for 6-bit, 63 comparators.,AD/DA (v.5b),31,Type 5 ADC : subranging Flash ADC,Compromise; medium speed Pure Flash ADC is very expensive for large number of bits. Subrang
21、ing Flash ADC is Hybrid between successive approximation and flash. AD7280 or ADC0820 uses two 4-bit flash ADC to build an 8-bit subranging Flash ADC. Figure next page: Upper 4-bit (MSB) flash ADC finds coarse MSB digital output, then converts into approximate analog level by a 4-bit DAC, the lower
22、4-bit flash ADC finds the fine 4-bit (LSB) digital code.,AD/DA (v.5b),32,Diagram of a subranging Flash built from two 4-bit flash ADC, 1,Exercise 3.5 subranging Flash ADC,Discuss the conversions for the following cases Bit7,Bit0 0000 0000=_ 0000 0001=_ 1010 1010=_ 1111 1111=_,AD/DA (v.5b),33,AD/DA (
23、v.5b),34,Sampling and hold?,Signal Voltage Vin Vin(t1)sampling,Sample and,Hold and convert signal into data n,Data n generated,t1,Vin(t1) held and being converted,time,A fast changing signal,Why? It is because when a slow ADC is used to sample a fast changing signal only a short sampling point can b
24、e analyzed,AD/DA (v.5b),35,Sampling-speed limitation,Given the conversion time of an ADC is Tconv seconds, the maximum sampling rate is Fmax=1/T (Hz) . E.g: ADC0801, Tconv =114ns+P to ADC delay, Fmax 8.77KHz For this sample rate the maximum frequency for the input is (Fmax/2) 4.39KHz by Nyquist samp
25、ling theory. Need to use a sample-and-hold circuit to freeze a fast changing input when using a low speed ADC to convert the signal. For high speed conversion, use Direct-Memory-Access (DMA) to copy the data directly to P memory to reduce P to ADC delay.,AD/DA (v.5b),36,Frequency aliasing,When the h
26、ighest frequency of the signal Finput is greater than half the sampling ( Fsampling/2). E.g. Finput =20KHz, Fsampling must be over 40KHz. Remedy: Use a low pass filter to cut off the input high frequency content before ADC sampling.,AD/DA (v.5b),37,upper = sampling 6 times per cycle(fs=6f); middle =
27、 sampling 3 times per cycle(fs=3f); lower= sampling 6 times in 5 cycles, from1,AD/DA (v.5b),38,Method to reduce aliasing noise,ADC Sampling at 40KHz,output code = n 0110001 0100010 0100100 0101011 : : :,Input voltage = V,Low Pass Filter: fcorner=20KHz,e.g. Max freq =20KHz,Use low pass filter to remo
28、ve high frequency before sampling,Freq.,Gain(dB),0 -3dB cut off,Exercise 3.6,If a signal is ranging from 30Hz to 100KHz, what is the suitable sampling rate for the ADC to be used. Answer:_ If noise exists in the surrounding, what should you do to ensure the conversion is accurate? Answer: _,AD/DA (v
29、.5b),39,AD/DA (v.5b),40,Commercially available multiple input channels ADC board with channel select and sample-and-hold,AD/DA (v.5b),41,Practical ADCs,Low cost, low speed (successive approximation, 8bit-8KHz sampling), National semiconductor ADC0801,2,3,4 family. See http:/ Medium speed (half-flash
30、, 8-bit 666KHz), National semiconductor ADC0820. High speed (flash 8-bit,4080MHz, video quality) Philips TDA8714 (/7/6/4) family. See http:/207.87.19.21/products/,AD/DA (v.5b),42,ADC0801 description from http:/ successive approximation A/D converters that use a differential potentiometric ladder-sim
31、ilar to the 256R products. Output latches directly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed.Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input vo
32、ltage value. Voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.,AD/DA (v.5b),43,ADC0801 features,Compatible with 8080 P derivatives-no interfacing logic needed - access time - 135 ns Easy interface to all microprocessors, or op
33、erates “stand alone“ . Differential analog voltage inputs Logic inputs and outputs meet both MOS and TTL voltage level specifications Works with 2.5V (LM336) voltage reference On-chip clock generator 0V to 5V analog input voltage range with single 5V supply No zero adjust required 0.3FootMinutePrime
34、 standard width 20-pin DIP package 20-pin molded chip carrier or small outline package Operates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference,AD/DA (v.5b),44,ADC0820 half-flash ADC, from http:/ half-flash 8-bit ADC0820 A/D offers a 1.5 s conversion time The half-f
35、lash technique consists of 32 comparators, a most significant 4-bit ADC and a L.S. 4-bit ADC.The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/s. For ease of interface to microproce
36、ssors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.,AD/DA (v.5b),45,ADC0820 features,Built-in track-and-hold function No missing codes , no external clocking Single supply-5 VDC. Easy interface to all microprocessors, or op
37、erates stand-alone Latched TRI-STATE output Logic inputs and outputs meet both MOS and T2L voltage level specifications Operates ratiometrically or with any reference value equal to or less than VCC 0V to 5V analog input voltage range with single 5V supply No zero or full-scale adjust required Overf
38、low output available for cascading,AD/DA (v.5b),46,Exercise 3.7. Discuss the technology used in making the built-in ADC and DAC in LPC2131 (Philips ARM7 microcontroller) www.hitex.co.uk http:/ ANSWER: _,One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total of up to 16 analog
39、inputs, with conversion times as low as 2.44 us per channel. A single 10-bit DAC provides variable analog output (LPC2132/34/36/38).,AD/DA (v.5b),47,Exercise 3.8 :,Discuss the estimated error in voltage when using this ADC. From the datasheet: One (LPC2131/32) as low as 2.44 us per channel. Can you
40、estimate the sampling rate? Answer:_,ADC characteristic in LPC2131,(1) Actual transfer curve,(2) ideal,AD/DA (v.5b),48,Summary,Studied the operations of Digital/analogue conversions. Studied the application of Digital/analogue converters.,AD/DA (v.5b),49,References,1 Interfacing: A Laboratory Approach Using the Microcomputer for Instrumentation, Data Analysis, and Control by Stephen E. Derenzo 2 http:/
