1、The Design Process,Outline Design Domain Design Flow Behavioral Design Structural Design Physical Design Management of ComplexityGoal Understand phases of design process Understand complexity management Understand where tools are needed,Design Domain,Physical Domain,Behavioral Domain,Structural Doma
2、in,App,OS,Prog,Proc,Inst,Xistor,Cell,Module,Board,Box,Field,Xistor,Gate,RTL,CPU,PMS,Architecture,Logic,Circuit,Process,Design Flow,Behavioral Design,Structural Design,Physical Design,Manufacturing Specification,Design Specification,Mapping,Mapping,Simulation Design Rule Checking,Verification Functio
3、n Speed, Power,Verify Function,Verify Function,Sim., DRC,Sim., DRC,Feedback,Manuf. Data,Design Phase,Synthesis,Analysis,Verification Validation,Upper Design Level,Lower Design Level,Reject,Reject,Map to more detailed design representation.,Determine if design meets performance objectives, obeys manu
4、facturing rules.Often contained as part of synthesis tool inner loop.,Determine if equivalent to more abstract design. Human error or tool bug if not.,Usually just rework design,Might require starting over,Behavioral Design,Map design spec to formal behavioral description design spec = user desires
5、“a cheap 100MHz Pentium chip” often not formally described design and behavioral spec often developed together Approach use behavioral hardware description language (HDL) Verilog VHDL HDL is programming language superset support for timing, modules verify HDL implements design spec usually through s
6、imulation check that HDL is self-consistent “compile” and simulate,Structural Design,Map behavioral spec to structural spec partition into functional blocks - the netlist targets for eventual physical design Approach use behavioral modules as starting point decompose each block to finer detail funct
7、ion to gates to transistors, etc. stop at manufacturing interface logic design - boolean equations = gates simulation to verify structure has correct behavior interconnect verification design rule checking feedback from physical design - back annotation for performance verification,RegA,+,RegB,c = a
8、 + b,RegC,Physical Design,Map from structure to physical implementation target technology technology mapping netlist to 2-D layout Approach partition into boards, modules, chips, cells, layout place and route fix cell locations route wiring cell layout design rule checking circuit extraction interco
9、nnect verification back annotation,Management of Complexity,Bigger, faster designs have more coupling in design flow more feedback = more design iterations = higher cost simultaneous design = complex tools cannot do “technology independent” design Typical big design 10M transistors 300 MHz clock rat
10、e beyond brute force approaches Solutions hierarchy regularity abstraction simplification,Hierarchy,Structure design as you would a program “procedure calls” stop at manufacturing interface - “atoms” of IC universe,P,Datapath,Cache,ALU,Shift,Reg,Mult,I/O,SRAM,1-Bit ALU,Use ALU cell from library,Desi
11、gn SRAM cell by hand,Regularity,Use replication behavioral - call same procedure many times structural - instantiate same cell many times physical - instantiate same cell many times Examples bit in SRAM array bit slice in datapath Enhancement module generators procedure call for structural and physi
12、cal design pitch matching array logic PLA, ROM,Abstraction,Use most abstract representation possible hide information = less memory simpler representation = less CPU time to generate to analyze! Generate information only as needed cost too high to generate and discard Accuracy-cost tradeoff never en
13、ough resources for full verification performance prediction optimization,Simplification,Restrict design space restrict technology only single-poly, double-metal CMOS restrict circuit family only digital only complementary gates restrict design style only gate array Restrict object types only rectang
14、ular mask geometry no overlapping layout cells,Implications for EDA Tool Design,Support the design flow but tools also determine the design flow Limit domain but entire application range must be covered Restrict representations a tool box, not a Swiss Army knife Bridge domains verification - e.g. logic vs. layout concurrent design Bridge representations verification - e.g. netlist vs. geometry sufficient accuracy with acceptable speedEDA tools must meet designers needs,
