1、INTERNATIONAL STANDARD ISOAEC 11458 1993 i AMENDMENT 1 2000-07 Amendment 1 Information technology - Microprocessor systems - VICbus - Inter-crate cable bus Amendement I Technologies de linformation - Systmes microprocesseurs - VICbus - Bus cbles inter-chssis fliis material is reproduced from IS0 doc
2、uments under Iiiteriiatioiial Organization f Standardization (EO) Copyriglit License Nuinber HIS/CC/1996. Not for resale. No part of these IS0 documents may be reproduced iii any form, electronic retrieval system or otherwise, except as allowed iii the copyright law of the country of use, or with th
3、e prior writteii consent of IS0 (Case postale 56,121 I Geneva 20, Switzerland, Fax +4i 22 734 i0 79), IHS or the IS0 Licensors iiicmbers. ISO/IEC 2000 All rights resewed. Unless otherwise specified. no part of this publication may be reproduced or utilized in any form or by any means, electronic or
4、mechanical. including photocopying and microfilm. without permission in writing from the publisher. ISO/IEC Copyright Office Case postale 56 CH-121 1 Genve 20 Switzerland PRICECODE B For price, see current catalogue -2- 11458 Amend. 1 O ISO/IEC:2000(E) FOREWORD Amendment 1 to International Standard
5、ISOAEC 11458 was prepared by subcommittee 26: Microprocessor systems, of ISO/IEC joint technical committee 1 : Information technology. A horizontal line in the margin indicates where the text has been changed with respect to the original table. e r Page 69 Table 21 - VICbus connector pin assignments
6、 Replace the existing table 21 by the following new table: 4 e 9 11 IDO+ 10 IDO- ID1+ 12 ID1- 11 13 INTSELO+ 12 INTSELO- VICRESET+ 14 VICRESET- 13 15 ID2+ 14 ID2- ID3+ 16 ID3- 15 17 BR+ 16 BR- GROUND 18 GROUND 19 21 DEVFAIL+ 20 DEVFAIL- BGIN+ (VC2-i) 22 BGIN- (VC2-i) BGOUT+ (VC2-O) BGOUT- (VC2-O) 23
7、 25 CL1+ 24 CL1- INTO+ 26 INTO- 25 27 INT4+ 26 INT4- INT5+ 28 INT5- 27 29 INTl+ 28 INT1- INT2+ 30 INT2- 31 33 INT3+ 32 INT3- ADOO+ 34 ADOO- 35 37 ADO1+ 36 ADO1- AD02+ 38 AD02- 39 41 AD03+ 40 AD03- AD04+ 42 AD04- 51 53 AD09+ 52 AD09- AD10+ 54 AD10- 51 53 AD25+ 52 AD25- AD26+ 54 AD26- 55 57 AD11+ 56 A
8、D11- AD12+ 58 AD12- 55 57 AD27+ 56 AD27- AD28+ 58 AD28- 59 61 AD13+ 60 AD13- AD14+ 62 AD14- 59 61 AD29+ 60 AD29- AD30+ 62 AD30- 63 AD15+ 64 AD15- Table 21 - VICbus connector pin assignments Connectors VCl -i and VCl -o Connectors VC2-i and VC2-o 1D4- BGLOOP+ BGLOOP- Pin I Line I Pin I Line 1 IAP+ I
9、2 IAP- 5 IAS+ I 6 IAS- 7 IDS+ I 8 IDS- SERR+ SERR- 9 I BBSY+ I 10 I BBSY- 1 CLO+ 22 CLO- 23 I INTSELl+ I 24 I INTSELI- 29 1 INT6+ I 30 I INT6- 31 I INT7+ I 32 1 INT7- 43 1 AD05+ I 44 AD05- AD06- AD07- AD08- AD08+ AD22+ AD22- 47 1 AD23+ I 48 1 AD23- 49 I AD24+ 1 50 I AD24- 63 1 AD31+ I 64 1 AD31- ISB
10、N 2-831 8-5343-5 4 ICs 35.160 Typeset and printed by the IEC Central Office GENEVA, SWITZERLAND IS0 LI458 73 485L903 0550365 L II INTERNATIONAL ISOIIEC STANDARD 11 458 First edition 1993-1 2-01 Information technology - Microprocessor systems - VICbus - Inter-crate cable bus Technologies de linformat
11、ion - Systmes microprocesseurs - VICbus - Bus cbles inter-chssis Reference number ISOAEC 11458: 1993(E) CONTENTS Page FOREWORD 7 Clause 1 Scope . 8 Introduction to the ISO/IEC 11458 VICbus standard . 9 2.2 Standard terminology . 9 2.2.3 Permission . 10 2.2.4 Observation . 9 2.2.2 Recommendation 9 3
12、3.2 3.2.1 Direct cycles 12 Use of the DTB information lines . 13 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.1 O 3.3.1 1 3.3.1 2 3.3.13 3.3.1 4 3.3.15 3.3 Write signal WRITE 16 Interrupter number signals IN4-IN0 18 Data signals D31-DOO 18 3.4 3.5 3.5.1 3.5.2 Read-modify-write cycles .
13、19 3.6.1 3.6.2 3.7.1 3.7.2 Non-compelled 2 (NC2) . 27 3.8 O ISOIIEC 1993 All rights reserved . No pari of this publication may be reproduced or utilized in any form or by any means. electronic or mechanical. including photocopying and microfilm. without permission in writing from the publisher . ISO
14、IIEC Copyright Office Case Postale 131 CH-1211 Genve 20 Switzerland Printed in Switzerland IS0 LL45B 93 881 4453903 0550367 TbL ISO/IEC 11458 : 1993 -3- 3.9 DIB timing rules 29 Arbitration 41 4.1 introduction 41 4.2 Lines 41 4.3 Arbitration protocol . 41 4.4 Arbiter . 42 4.5 Requester 43 4.6 Transfe
15、r of DTB mastership . 43 4.7 Loss of the arbiier 44 4.8 Arbitration timing rules . 48 Interrupts 50 5.1 Introduction 50 5.2 Lines and signals . 50 5.3 Interrupt request signal selection . 50 5.4 Interrupt protocol 51 5.5 Interrupter 52 5.6 Interrupt handler . 53 5.7 Timing regulations . 55 tilrties
16、. . 57 6.1 6.2 6.3 6.4 6.5 6.6 Introduction 57 6.1.1 Arbitration lock line ALOCK 57 6.1.2 Device failure line DEVFAIL . 57 6.1.3 Intempt request select lines INTSELO and INTSEL1 57 6.1.4 VICbus reset line VICRESET . 58 INTSEL generator selection . 58 Reset 61 6.3.1 Global reset - VICRESET 61 6.3.2 S
17、elective reset . 61 Online and off line states 62 6.4.1 Regulations 63 6.4.2 Power-up condaion 64 Faun tolerance . 64 Cable connection and disconnection in robust systems 65 Electrical specifications 66 7.1 Introduction 66 7.2 Bus drivers and receivers 66 7.3 Cables 67 7.3.1 Cable characteristics 68
18、 7.4 Connectors . 68 7.5 Terminators 70 7.5.1 Arbitration daisy-chain (BG line) termination 70 7.5.2 Terminator power . 70 7.5.3 Terminators and BGLWP . 70 7.6 Cable continuity for off line devices 72 VICbus registers 74 8.1 Introduction 74 8.2 Register summary 74 8.3 Control and status register . C
19、SR 75 8.4 Online register . OLR . 76 8.5 Device operational register . DOR . 77 8.6 Reset register . RR 78 IS0 11458 73 4851903 05503b8 7T8 -4- O ISOIIEC 11 458 : 1993 8.7 8.8 Transparent register . TR . 79 Device identification registers - DIR . 80 Annexes A B C D E F Interfacing between VMEbus and
20、 VICbus . 82 A . 1 A.2 A.3 A.4 A.5 Introduction 82 Address and data . 83 A.2.4 VMEbus RETRY . 84 A.2.7 Block transfers . 84 Utilities . 87 Data transfer bus . 83 A.2.1 A.2.2 VMEbus AM codes 83 A.2.3 VICbus slave response 83 A.2.5 VMEbus 064 transfers . 84 A.2.6 VMEbus address only cycles . 84 Interr
21、upts 86 A.4.1 System failure 87 A.4.2 System reset 88 VMEbus interface functions . 89 . Glossary 90 Summary of lines and signals 93 Arbitration dead lock 95 Wired-OR glitch . 96 VICbus electrical characteristics 97 F.l F.2 Electrical termination 97 Practical VICbus implementations . 98 IS0 11458 93
22、B 4851703 0550369 834 O ISO/IEC 11458 : 1993 -5- Page Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A.1 VICbus data representation . 10 Direct cycles . 12 Transparent cycles . 12 Use of the address /data, control and identification lines 15 VMEbus byte align
23、ment . 17 Byte lane alignment . 17 Transparent VME-A64 signal assignment 18 Summary of slave participation in DTB cycles . 28 Master - timing regulations . 36 Slave - timing regulations . 39 Arbiter - timing regulations . 48 Requester - timing regulations . 49 Interrupt request multiplexing 50 IACK
24、byte alignment 52 Summary of interrupt protocol actions . 54 Interrupts - timing regulations . 56 INTSEL generator selection - timing regulations . 60 Summary of the online / offline state of a device following various actions . 62 Summary of actions permitted in the three online / off line states .
25、 62 VICbus lines . 67 VICbus connector pin assignments 69 Register summary 74 Command and status register . 75 Device operational register 77 Online register 76 Reset register . 78 Transparent register . 79 Device identification registers - byte assignments . 80 Device identification register 2 - bi
26、t assignments . 81 Device identification register 3 - bit assignments . 81 VMEbus interface control and status functions 89 IS0 11458 93 El 4851903 0550370 556 El! -6- O ISO/IEC 11458 : 1993 Page Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A . 1 A . 2 A.3 D.l E . 1 F . 1 F.2 DTB cycle 13 Co
27、mpelled protocol 20 Non-compelled 1 protocol 24 Non-compelled 2 protocol 26 Compelled cycle . 30 Compelled cycle last data transfer and end of cycle 31 NC1 address phase and first data transfer 32 NC1 last data transfer and end of cycle . 33 NC2 address phase and first data transfer 34 NC2 last data
28、 transfer and end of cycle . 35 Arbitration-1 . 45 Arbitration-2 . 46 Arbitration3 . 47 INTSEL generator selection . 59 Electrical transmission . 71 Interrupt request selection timing . 55 Bus grant daisychain and BGLOOP . 72 Bus Grant termination and continuity of lines in robust systems . 73 Inter
29、-crate block transfers 85 DEVFAIL / SYSFAIL interconnection for a VMEbus to VICbus interfa ce . 87 Reset circuit for a VMEbus to VICbus interface . 88 Arbitration dead-lock resolution . 95 Wired-OR glitch 96 VICbus termination 97 Device / cable length derating . 98 IS0 11458 93 E3 4853903 0550373 49
30、2 H O ISO/IEC 11458 : 1993 -7- Foreword IS0 (the International Organization for Standardization) and IEC (the International Electrotechnical Commission) form the specialised system for world-wide standardisation. National bodies that are members of IS0 or IEC participate in the development of Intern
31、ational Standards through technical committees established by the respective organisation to deal with particular fields of technical activity. IS0 and IEC technical committees collaborate in fields of mutual interest. Other international organisations, governmental and non-governmental, in liaison
32、with IS0 and IEC, also take part in the work. In the field of information technology, IS0 and IEC have established a joint technical committee, ISOAEC JTC1. Draf International Standards adopted by the joint technical committee are circulated to national bodies for voting. Publication as an Internati
33、onal Standard requires approval by at least 75 % of the national bodies casting a vote. International Standard ISOIIEC 11458 was prepared by Joint technical committee ISOAEC JTC 1, Information technology, SC 26: Microprocessor Systems. Annex A forms an integral pari of ISOAEC 1 1458. Annexes B to F
34、are for information only. IS0 11458 93 1yI Y851903 0550372 329 O ISOIIEC 11458 : 1993 -8- Information technology - Microprocessor systems - VICbus - Inter-crate cable bus 1 scope The widespread use of high-performance, multi-processor systems based on backplane buses such as the IEC 821 bus (VMEbus)
35、, has inevitably led to the requirement to create multi-crate (-subrack, -chassis, etc.) systems. The VICbus inter-crate cable bus is designed to achieve such assemblies in a standard way. VICbus, a multiplexed, multi-master, multi-slave cable bus, connects multiple backplane buses or stand-alone de
36、vices, providing transparent, softwareless interconnection for low latency short data transactions and fast transmission of data blocks over cables of up to 1 O0 m in length. Address and data signals, each of 32 bits, together with those necessary for the control of the bus protocols, signal multipl
37、exing, reset and error reporting are transmitted on twisted-wire pairs using differential line drivers and receivers. Up to 31 devices are permitted on a single VICbus cable. VICbus data transfer protocols include both a compelled mode with end-to-end acknowledgement as well as two, high speed, non-
38、compelled modes for high rate data transfers. The compelled protocols allow both broadcast (master write) and broadcall (master read) data transfers. One of the non- compelled protocols allows broadcast transfers, whereas neither permit broadcall operation. Inter-master arbitration uses an efficient
39、, modified single-level, daisychained mechanism. The interrupt mechanism allows 32 interrupt requests, multiplexed on eight physical lines. The specification includes system failure reporting, reset and live connection and disconnection, as well as the specification of control and status registers.
40、Particular attention has been paid to redundancy . of operation. Whilst VICbus has been derived with multicrate backplane bus systems in mind, this specification does not preclude the design of stand-alone VICbus devices. A normative annex giving rules and recommendations for a VMEbus to VICbus inte
41、rface has been included, and further, similar annexes for other backplane bus standards will be added as the need arises. IS0 11458 93 t!?3 4851903 0550373 265 O ISO/IEC 11458 : 1993 -9- 2 2.7 Objectives VICbus is a cable bus intended to be used to connect together multiple devices, particularly bac
42、kplane bus systems, efficiently and with the possibility of software transparent operation, to allow large muiti-crate, muiti-processor systems to be constructed. The objectives of this standard are to: Introduction to the ISO/IEC 11458 VICbus standard a) provide a standard cable bus for the interco
43、nnection of multiple devices, both backplane bus systems, such as the IEC821 VMEbus, and stand-alone apparatus; b) specify the electrical characteristics of the cable bus; c) specify the protocols that precisely define the interaction between devices connected to the VICbus; d) spectfy the mechanism
44、s necessary to construct fault-tolerant, muiti-device systems; e) provide the necessary definitions, terminology and background information to fully describe the VICbus protocols and other mechanisms. 2.2 Standard terminology To avoid ambiguity, and to ensure that it is clear what the requirements f
45、or compliance are, many of the paragraphs in this standard are prefixed with sequentially numbered keywords by clause (N), known collectively as reguiations, thus: RECOMMENDATION tN.n* PERMISSION OBSERVATION cN.n 22.1 Rule Rules form the basis of the VICbus standard, and may be expressed in textual,
46、 diagrammatic or tabular form. They use the imperative form and include the upper case words SHALL or SHALL NOT, which are reserved for this purpose only. Rules are printed in italics, thus: RULE 2.1 Example: rules contain the upper case words SHALL or SHALL NOT. 2.2.2 Recommendation Recommendations
47、 contain information which will be very useful, if not vital, when designing to the VICbus standard and designers are encouraged to heed the advice given to ensure the best possible interpretation of the specifications requirements. RECOMMENDATION 2.1 Example: recommendations contain very useful inf
48、ormation. IS0 11458 93 L185L703 0550374 LTL 1111 Data bits - 10- Byte (0) Byto (1) Byte (2) Byte (3) 31 . 24 23 . 16 15 . 8 . O ISO/IEC 11458 : 1993 2.2.3 Permission Permissions clarify aspects of the standard where multiple choices might be possible, and indicate acceptable lines of approach. The u
49、pper case word MAY is reserved for this purpose only. PERMISSION 2.1 Example: permissions help you choose and include the upper case word MAY. 2.2.4 Observation dn Observations serve to explain the rationale behind rules and other requirements. OBSERVATION 2.1 Example: observations explain the rationale of certain requirements. 2.3 Other terminology All normative terms (that is those having a specified meaning within the context of this document) are typed in bold font, in general the first time they appear, thus: aMer. Such terms are explained in the informat
