1、IEEE Standard for Fault Accounting and Coverage Reporting (FACR) for Digital Modules IEEE Std 1804-2017 IEEE Computer Society Sponsored by the Test Technology Standards Committee IEEE 3 Park Avenue New York, NY 10016-5997 USAIEEE Std 1804-2017 IEEE Standard for Fault Accounting and Coverage Reportin
2、g (FACR) for Digital Modules Sponsor Test Technology Standards Committee of the IEEE Computer Society Approved 6 December 2017 IEEE-SA Standards BoardAbstract: Aspects of fault models as they are relevant to the generation of test patterns for digital circuits are formalized in this standard. Fault
3、counting, fault classification, and fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model are included in the scope. It shall be incumbent for fault coverage to be reported in a uniform way on all ATPG tools (that comply with th
4、is standard). The generation of a uniform coverage (and, hence, a uniform test quality) metric for large chips including systems-on-chips (SOCs) with different cores and modules for which test patterns have been independently generated will be facilitated by this standard. Keywords: ATPG, fault mode
5、ls, fault simulation, IEEE 1804, semiconductor testing, stuck-at faults, test coverage The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA Copyright 2018 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published
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35、 reserved. Participants At the time this IEEE standard was completed, the FACR Working Group had the following membership: Rajesh Raina, Chair Rubin Parekhji, Vice Chair Saman Adham Srinivasulu Alampally Greg Aldrich Brady Benware Sudipta Bhawmik Richard Billings Jeff Bosworth Kenneth Butler Vivek C
36、hickermane Aloke Das Grazia Delia Charu Dixit Stefan Eichenberger Vijay Gangaram Larry Gilg Andreas Glowatz Arun Gunda Ismed Hartanto Kazumi Hatayama Cy Hay Brion Keller Ajay Koche Prabhu Krishnamurthy Mary Kusko Fadi Maamari Rajat Mehrotra Subhasish Mitra Phil Nigh Bill Price Ashu Razdan Jeff Reari
37、ck Michael Reese Colin Renfrew Jyotirmoy Saikia Vaskar Sarkar Mike Tripp Hans Tsai Devanathan V aradarajan Duncan (Hank) Walker Ronald Walther LeRoy Winnemberg Shianling Wu Mahmut Yilmaz Greg Y oung The following members of the individual balloting committee voted on this standard. Balloters may hav
38、e voted for approval, disapproval, or abstention. Saman Adham Bakul Banerjee Kenneth Butler Juan Carreon Vivek Chickermane Keith Chow Adam Cron Heiko Ehrenberg William Eklow Randall Groves Peter Harrod Werner Hoelzl Rohit Kapur Yuri Khersonsky Adam Ley Teresa Lopes Gregory Maston Jeffrey Moore Micha
39、el Newman Charles Ngethe Rubin Parekhji Ulrich Pohl Rajesh Raina Michael Reese Mike Ricchetti Walter Struppler Kun-Han Tsai Devanathan V aradarajan Oren Y uen When the IEEE-SA Standards Board approved this standard on 6 December 2017, it had the following membership: Jean-Philippe Faure, Chair Gary
40、Hoffman, Vice Chair John D. Kulick, Past Chair Konstantinos Karachalios, Secretary Chuck Adams Masayuki Ariyoshi Ted Burse Stephen Dukes Doug Edwards J. Travis Griffith Michael Janezic Thomas Koshy Joseph L. Koepfinger* Kevin Lu Daleep Mohla Damir Novosel Ronald C. Petersen Annette D. Reilly Robby R
41、obson Dorothy Stanley Adrian Stephens Mehmet Ulema Phil Wennblom Howard Wolfman Y u Y uan *Member Emeritus7 Copyright 2018 IEEE. All rights reserved. Introduction This introduction is not part of IEEE Std 1804-2017, IEEE Standard for Fault Accounting and Coverage Reporting (FACR) for Digital Modules
42、. Like any manufacturing process, digital circuits are susceptible to various defects. Shorted or open wire connections are common defect examples. Leakier gate to drain channel in a transistor is one example of a complex defect. Fault models are defined to abstract and represent various defect mech
43、anisms. The fault models allow automatic test pattern generation (A TPG) during the digital circuit design phase using a process called Fault Simulation. Fault Grading is the process of gauging the effectiveness of ATPG in detecting the modeled faults. The most common and prevalent fault model is th
44、e single stuck-at fault modelprimarily due to its simplicity and effectiveness in representing a large class of physical defects. The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fau
45、lt classification, and c) fault coverage reporting across different ATPG tools for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform
46、coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated. The framework established by the standard should also allow developing fault accounting standards for other fault models in the future. This may include delay defects and reliability failures while including different ways of representing digital circuits, such as VHDL, and with different levels of abstraction.
