1、 INTERNATIONAL STANDARD IEC61523-3First edition2004-09IEEE 1497 Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process Reference number IEC 61523-3(E):2004 IEEE Std. 1497(E):2001 Publication numbering As from 1 January 1997 all IEC publications ar
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8、ulation standards Part 3: Standard Delay Format (SDF) for the electronic design process INTERNATIONAL STANDARD IEC61523-3First edition2004-09IEEE 1497Commission Electrotechnique InternationaleInternational Electrotechnical Commission IEEE 2004 Copyright - all rights reserved IEEE is a registered tra
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15、en processed through IEC technical committee 93: Design automation. The text of this standard is based on the following documents: IEEE Std FDIS Report on voting 1497 (2001) 93/191/FDIS 93/196/RVD Full information on the voting for the approval of this standard can be found in the report on voting i
16、ndicated in the above table. This publication has been drafted in accordance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2006. IEC 61523 consists of the following parts, under the general title Delay and power calculation s
17、tandards: IEC 61523-1, Part 1: Integrated circuit delay and power calculation systems Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E)IEEE 1497-2001(E) 3 IEC 61523-2, Part 2: Pre-layout delay calculation specification of CMOS ASIC libraries IEC/IEEE 61523
18、-3, Part 3: Standard Delay Format (SDF) for the electronic process Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E)IEEE 1497-2001(E) 4 IEC/IEEE Dual Logo International Standards This Dual Logo International Standard is the result of an agreement between t
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37、ed by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention. Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E)IEEE 1497-2001(E) 5 IEEE Standard for Standard Delay Format (SDF) for t
38、he ElectronicDesign ProcessSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 5 December 2001IEEE-SA Standards BoardAbstract:The Standard Delay Format (SDF) is defined in this standard. SDF is a textual file formatfor representing the delay and timing information of elec
39、tronic systems. While both human andmachine readable, in its most common usage it will be machine written and machine read in supportof timing analysis and verification tools, and of other tools requiring delay and timing information.The primary audience for this standard is the implementors of tool
40、s supporting the format, butanyone with a need to understand the formats contents will find it useful.Keywords:computer, computer languages, delay, delay backannotation, digital systems, electron-ic systems, hardware, hardware design, SDF, timing, timing analysis, timing backannotation, timingverifi
41、cationPublished by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61523-3:2004(E)IEEE 1497-2001(E) 6 Copyright 2001 IEEE. All rights reserved.iiiThe Standard Delay Format (SDF) was designed to serve as a simple textual medium for communicatingtiming information and constraints betw
42、een EDA tools. The original version was designed by Rajit C. Chan-dra in 1990 while at Cadence Design Systems, and was intended as a means of communicating macrocelland interconnect delays from Gate Ensemble to Verilog-XL, Veritime and other stand-alone tools requiringtiming data.Because it was orig
43、inally targeted for annotation to tools using the Verilog language, many SDF constructsare analogous to those in Verilog specify blocks. Those already familiar with the Verilog specify block willnd many of the SDF constructs familiar, such as SETUP and PATHPULSE. SDF also includes constructsfor anno
44、tating interconnect delays, and can be used for forward annotation by specifying path delay con-straints from timing analysis to oorplanners, and synthesis and layout tools.SDF was rst introduced into the EDA marketplace in 1991 where it won quick acceptance. Cadence placedSDF in the public domain i
45、n 1992 when it turned control over to Open Verilog International (OVI), and OVIdelivered the rst SDF standard, version 2.0, in June, 1993 (SDF version 1.0 was used by Cadence). OVI hassince introduced version 2.1 in February, 1994, and version 3.0 in May, 1995. VHDL (IEEE 1076) also takesadvantage o
46、f SDF through the VITAL standard.In 1996 the OVI Board of Directors began an effort to establish SDF as an IEEE standard. With the approvalof the IEEE Design Automation Standards Committee (DASC), the OVI Logic Modeling Technical Sub-committee became the IEEE SDF Study Group. With the approval of th
47、e Project Authorization Request(PAR) by the IEEE Standards Board on February 10, 1997, this group became the IEEE SDF WorkingGroup.This IEEE SDF standard builds upon OVI SDF version 3.0, and will be known as version 4.0. The changesfrom OVI 3.0 to IEEE 4.0 are small (LABEL construct added, NETDELAY
48、construct restored), but thechange from OVI standard to IEEE standard is signicant, and so this is recognized by a new versionnumber.ObjectiveThe starting point for the IEEE P1497 SDF Working Group was the OVI LRM version 3.0 SDF standard,with the goal of soliciting further enhancements and improvin
49、g the quality and rigor of the LRM. Since SDFis already in widespread use, no modications that would invalidate current usage were considered.AcknowledgmentsThis standard is based on work originally developed by Cadence Design Systems, Inc. (in SDF 1.0) andOpen Verilog International (in SDF 2.0, 2.1 and 3.0). The IEEE is grateful to Cadence Design Systems andOpen Verilog International for permission to use their materials as the basis for this standard.Published by IEC under licence from IEEE. 2004 IEEE
