1、 INTERNATIONAL STANDARD IEC62142First edition2005-06IEEE 1364.1Verilogregister transfer level synthesis Reference number IEC 62142(E):2005 IEEE Std. 1364.1(E):2002 Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 60000 series. For example, IEC 34
2、-1 is now referred to as IEC 60034-1. Consolidated editions The IEC is now publishing consolidated versions of its publications. For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendment 1 and the base publication incorpo
3、rating amendments 1 and 2. Further information on IEC publications The technical content of IEC publications is kept under constant review by the IEC, thus ensuring that the content reflects current technology. Information relating to this publication, including its validity, is available in the IEC
4、 Catalogue of publications (see below) in addition to new editions, amendments and corrigenda. Information on the subjects under consideration and work in progress undertaken by the technical committee which has prepared this publication, as well as the list of publications issued, is also available
5、 from the following: IEC Web Site (www.iec.ch) Catalogue of IEC publications The on-line catalogue on the IEC web site (www.iec.ch/searchpub) enables you to search by a variety of criteria including text searches, technical committees and date of publication. On-line information is also available on
6、 recently issued publications, withdrawn and replaced publications, as well as corrigenda. IEC Just Published This summary of recently issued publications (www.iec.ch/online_news/ justpub) is also available by email. Please contact the Customer Service Centre (see below) for further information. Cus
7、tomer Service Centre If you have any questions regarding this publication or need further assistance, please contact the Customer Service Centre: Email: custserviec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 Verilogregister transfer level synthesis INTERNATIONAL STANDARD IEC62142First edition200
8、5-06IEEE 1364.1Commission Electrotechnique InternationaleInternational Electrotechnical Commission IEEE 2005 Copyright - all rights reserved IEEE is a registered trademark in the U.S. Patent any IEC National Committee interested in the subject dealt with may participate in this preparatory work. Int
9、ernational, governmental and non-governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two organizations. 2) The f
10、ormal decisions or agreements of IEC on technical matters express, as nearly as possible, an international consensus of opinion on the relevant subjects since each technical committee has representation from all interested IEC National Committees. 3) IEC Publications have the form of recommendations
11、 for international use and are accepted by IEC National Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any misinterpretation by any end user
12、. 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications transparently to the maximum extent possible in their national and regional publications. Any divergence between any IEC Publication and the corresponding national or regional publication s
13、hall be clearly indicated in the latter. 5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any equipment declared to be in conformity with an IEC Publication. 6) Attention is drawn to the possibility that some of the elements of this IEC Publication
14、 may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC/IEEE 62142 has been processed through IEC technical committee 93: Design automation. The text of this standard is based on the following documents: IEEE S
15、td FDIS Report on voting 1364.1 (2002) 93/213/FDIS 93/218/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. Verilogis a registered trademark of Cadence Design Systems, Inc. This publication has been drafted in acco
16、rdance with the ISO/IEC Directives. The committee has decided that the contents of this publication will remain unchanged until 2007. IEC 62142:2005(E)IEEE 1364.1-2002(E) 4 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. IEC/IEEE Dual Logo International Standards This Dual
17、Logo International Standard is the result of an agreement between the IEC and the Institute of Electrical and Electronics Engineers, Inc. (IEEE). The original IEEE Standard was submitted to the IEC for consideration under the agreement, and the resulting IEC/IEEE Dual Logo International Standard has
18、 been published in accordance with the ISO/IEC Directives. IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Association (IEEE-SA) Standards Board. The IEEE develops its standards through a consensus development process,
19、approved by the American National Standards Institute, which brings together volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are not necessarily members of the Institute and serve without compensation. While the IEEE administers the process and establ
20、ishes rules to promote fairness in the consensus development process, the IEEE does not independently evaluate, test, or verify the accuracy of any of the information contained in its standards. Use of an IEC/IEEE Dual Logo International Standard is wholly voluntary. The IEC and IEEE disclaim liabil
21、ity for any personal injury, property or other damage, of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly or indirectly resulting from the publication, use of, or reliance upon this, or any other IEC or IEEE Standard document. The IEC and IEEE do not warran
22、t or represent the accuracy or content of the material contained herein, and expressly disclaim any express or implied warranty, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEC
23、/IEEE Dual Logo International Standards documents are supplied “AS IS”. The existence of an IEC/IEEE Dual Logo International Standard does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEC/IEEE Dual
24、 Logo International Standard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to change brought about through developments in the state of the art and comments received from users of the standard. Every IEEE Standard is subjected to review at least every
25、 five years for revision or reaffirmation. When a document is more than five years old and has not been reaffirmed, it is reasonable to conclude that its contents, although still of some value, do not wholly reflect the present state of the art. Users are cautioned to check to determine that they ha
26、ve the latest edition of any IEEE Standard. In publishing and making this document available, the IEC and IEEE are not suggesting or rendering professional or other services for, or on behalf of, any person or entity. Neither the IEC nor IEEE is undertaking to perform any duty owed by any other pers
27、on or entity to another. Any person utilizing this, and any other IEC/IEEE Dual Logo International Standards or IEEE Standards document, should rely upon the advice of a competent professional in determining the exercise of reasonable care in any given circumstances. Interpretations Occasionally que
28、stions may arise regarding the meaning of portions of standards as they relate to specific applications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiate action to prepare appropriate responses. Since IEEE Standards represent a consensus of concerned
29、 interests, it is important to ensure that any interpretation has also received the concurrence of a balance of interests. For this reason, IEEE and the members of its societies and Standards Coordinating Committees are not able to provide an instant response to interpretation requests except in tho
30、se cases where the matter has previously received formal consideration. Comments for revision of IEC/IEEE Dual Logo International Standards are welcome from any interested party, regardless of membership affiliation with the IEC or IEEE. Suggestions for changes in documents should be in the form of
31、a proposed change of text, together with appropriate supporting comments. Comments on standards and requests for interpretations should be addressed to: Secretary, IEEE-SA Standards Board, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331, USA and/or General Secretary, IEC, 3, rue de Varemb, P
32、O Box 131, 1211 Geneva 20, Switzerland. Authorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc., provided that the appropriate fee is paid to Copyright Clearance Center. To arrange for payme
33、nt of licensing fee, please contact Copyright Clearance Center, Customer Service, 222 Rosewood Drive, Danvers, MA 01923 USA; +1 978 750 8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through the Copyright Clearance Center. NOTE At
34、tention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEEE shall not be re
35、sponsible for identifying patents for which a license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention. IEC 62142:2005(E)IEEE 1364.1-2002(E) 5 Published by IEC under licence from IEEE. 2005 IEEE. All r
36、ights reserved. IEEE Standard for VerilogRegister Transfer Level SynthesisSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyApproved 10 December 2002IEEE-SA Standards BoardAbstract:Standard syntax and semantics for VerilogHDL-based RTL synthesis are described inthis standard.Key
37、words:hardware description language, HDL, RTL, synthesis, VerilogIEC 62142:2005(E)IEEE 1364.1-2002(E) 6 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. This standard describes a standard syntax and semantics for VerilogHDL-based RTL synthesis. It definesthe subset of IEEE S
38、td 1364-2001 (Verilog HDL) that is suitable for RTL synthesis and defines the seman-tics of that subset for the synthesis domain.The purpose of this standard is to define a syntax and semantics that can be used in common by all compliantRTL synthesis tools to achieve uniformity of results in a simil
39、ar manner to which simulation and analysistools use IEEE Std 1364-2001. This will allow users of synthesis tools to produce well-defined designswhose functional characteristics are independent of a particular synthesis implementation by making theirdesigns compliant with this standard.The standard i
40、s intended for use by logic designers and electronic engineers.Initial work on this standard started as a RTL synthesis subset working group under Open Verilog Interna-tional (OVI). After OVI approved of the draft 1.0 with an overwhelming affirmative response, an IEEEProject Authorization Request (P
41、AR) was obtained in July 1998 to clear its way for IEEE standardization.Most of the members of the original group continued to be part of the Pilot Group under P1364.1 to lead thetechnical work. The active members at the time of OVI draft 1.0 publication were as follows:J. Bhasker,Chair An approved
42、draft D1.4 was ready by April 1999, thanks very much to the efforts of the following taskleaders:When the working group was ready to initiate the standardization process, it was decided to postpone theprocess for the following reasons:a) The synthesis subset draft was based on Verilog IEEE Std 1364-
43、1995.b) A new updated Verilog language was imminent.c) The new Verilog language contained many new synthesizable constructs.It wasnt until early 2001 that Verilog IEEE Std 1364-2001 was finalized. The working group restarted theirwork by first looking at the synthesizability aspects of the new featu
44、res in the language. Thereafter, RAM/ROM modeling features and new attributes syntax were introduced into the draft standard.Many individuals from many different organizations participated directly or indirectly in the standardizationprocess. A majority of the working group meetings were held via te
45、leconferences with continued discussionson the working group reflector.Victor BermanDavid BishopVassilios GerousisDon HejnaMike QuayleAmbar SarkarDoug SmithYatin TrivediRohit VoraDavid Bishop (Web Admin.)Ken Coffman (Semantics)Don Hejna (Syntax) Doug Smith (Pragmas)Yatin Trivedi (Editor)IEEE Introdu
46、ctionIEC 62142:2005(E)IEEE 1364.1-2002(E) 7 Published by IEC under licence from IEEE. 2005 IEEE. All rights reserved. 1. Overview1.1 ScopeThis standard defines a set of modeling rules for writing VerilogHDL descriptions for synthesis. Adher-ence to these rules guarantees the interoperability of Veri
47、log HDL descriptions between register-transferlevel synthesis tools that comply to this standard. The standard defines how the semantics of Verilog HDLare used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the languagewith reference to what shall be suppo
48、rted and what shall not be supported for interoperability.Use of this standard will enhance the portability of Verilog-HDL-based designs across synthesis tools con-forming to this standard. In addition, it will minimize the potential for functional mismatch that may occurbetween the RTL model and th
49、e synthesized netlist.1.2 Compliance to this standard1.2.1 Model complianceA Verilog HDL model shall be considered compliant to this standard if the model:a) uses only constructs described as supported or ignored in this standard, andb) adheres to the semantics defined in this standard.1.2.2 Tool complianceA synthesis tool shall be considered compliant to this standard if it:a) accepts all models that adhere to the model compliance definition in 1.2.1.b) supports all pragmas defined in Clause 6.c) produces a
