1、 IEC 61188-5-4 Edition 1.0 2007-10 INTERNATIONAL STANDARD NORME INTERNATIONALE Printed boards and printed board assemblies Design and use Part 5-4: Attachment (land/joint) considerations Components with J leads on two sides Cartes imprimes et cartes imprimes quipes Conception et utilisation Partie 5
2、-4: Considrations sur les liaisons pistes-soudures Composants sorties en J sur deux cts IEC 61188-5-4:2007 THIS PUBLICATION IS COPYRIGHT PROTECTED Copyright 2007 IEC, Geneva, Switzerland All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any
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16、donner des commentaires sur cette publication ou si vous avez des questions, visitez le FAQ du Service clients ou contactez-nous: Email: csciec.ch Tl.: +41 22 919 02 11 Fax: +41 22 919 03 00 IEC 61188-5-4 Edition 1.0 2007-10 INTERNATIONAL STANDARD NORME INTERNATIONALE Printed boards and printed boar
17、d assemblies Design and use Part 5-4: Attachment (land/joint) considerations Components with J leads on two sides Cartes imprimes et cartes imprimes quipes Conception et utilisation Partie 5-4: Considrations sur les liaisons pistes-soudures Composants sorties en J sur deux cts INTERNATIONAL ELECTROT
18、ECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE N ICS 31.180 PRICE CODE CODE PRIX ISBN 2-8318-1061-5 Registered trademark of the International Electrotechnical Commission Marque dpose de la Commission Electrotechnique Internationale 2 61188-5-4 IEC:2007 CONTENTS FOREWORD.3 INTRODUCTIO
19、N.5 1 Scope.6 2 Normative references .6 3 General information6 3.1 General component description .6 3.2 Marking .7 3.3 Packaging .7 3.4 Process considerations .7 4 Small outlined J packages (SOJ)7 4.1 Component description7 4.2 Component dimensions .8 4.3 Solder joint fillet design .9 4.4 Land patte
20、rn dimensions .11 Bibliography15 Figure 1 SOJ construction8 Figure 2 SOJ component dimensions.9 Figure 3 Solder joint fillet design11 Figure 4 SOJ land pattern dimensions .14 61188-5-4 IEC:2007 3 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ PRINTED BOARDS AND PRINTED BOARD ASSEMBLIES DESIGN AND USE P
21、art 5-4: Attachment (land/joint) considerations Components with J leads on two sides FOREWORD 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to
22、promote international co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports, Publicly Available Specifications (PAS) and Gui
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30、nce upon, this IEC Publication or any other IEC Publications. 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is indispensable for the correct application of this publication. 9) Attention is drawn to the possibility that some of the el
31、ements of this IEC Publication may be the subject of patent rights. IEC shall not be held responsible for identifying any or all such patent rights. International Standard IEC 61188-5-4 has been prepared by IEC technical committee 91: Electronics assembly technology This bilingual version, published
32、 in 2009-09, corresponds to the English version. The text of this standard is based on the following documents: FDIS Report on voting 91/703/FDIS 91/735/RVD Full information on the voting for the approval of this standard can be found in the report on voting indicated in the above table. The French
33、version of this standard has not been voted upon. 4 61188-5-4 IEC:2007 This publication has been drafted in accordance with the ISO/IEC Directives, Part 2. A list of all parts of the IEC 61188 series, under the general title Printed boards and printed board assemblies Design and use, can be found on
34、 the IEC website. The committee has decided that the contents of this publication will remain unchanged until the maintenance result date indicated on the IEC web site under “http:/webstore.iec.ch“ in the data related to the specific publication. At this date, the publication will be reconfirmed; wi
35、thdrawn; replaced by a revised edition, or amended. 61188-5-4 IEC:2007 5 INTRODUCTION This part of IEC 61188 covers land pattern for components with J leads on two sides. The proposed land pattern dimensions in this standard are based upon the fundamental tolerance calculation combined with the give
36、n land protrusions and courtyard excesses (see IEC 61188-5-1, Generic requirements). The courtyard includes all issues of the normal manufacturing necessities. The unaltered land pattern dimensions of this part are generally applicable for the solder paste application plus reflow soldering process.
37、For application of the wave soldering process (though uncommon for SOJ components) the land pattern and courtyard dimensions may have to be modified. An orientation parallel to the wave direction is strongly recommended and suitably dimensioned solder thieves should be added. This standard offers a
38、threefold land pattern dimensioning (levels 1, 2, 3) on the basis of a threefold set of land protrusions and courtyard excesses: maximum (max.); medium (mdn); and minimum (min.). Nevertheless the user may develop deviating land pattern dimensions based upon the methodology of IEC 61188-5-1, introduc
39、ing his own special material and assembling process conditions C, F, P and perhaps his own special land protrusions and courtyard excesses dimensions, as required. If a user has good reasons to use a concept different from that of IEC 61188-5-1 or if the user prefers unusual land protrusions, this s
40、tandard should be used for checking the resulting solder fillets. It is the responsibility of the user to verify his used SMD land patterns for achieving an undisturbed mounting process including testing and an ensured reliability for the product stress conditions in use. 6 61188-5-4 IEC:2007 PRINTE
41、D BOARDS AND PRINTED BOARD ASSEMBLIES DESIGN AND USE Part 5-4: Attachment (land/joint) considerations Components with J leads on two sides 1 Scope This part of IEC 61188 provides the component and land pattern dimensions for small outline integrated circuits with “J“ leads on two sides (SOJ componen
42、ts) used in the reflow soldering process. Basic construction of the SOJ device is also covered. Clause 4 lists the tolerances and target solder joint dimensions used to arrive at the land pattern dimensions. 2 Normative references The following referenced documents are indispensable for the applicat
43、ion of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60068-2-58, Environmental testing Part 2-58: Tests Test Td: Test methods for solderability, resistance to dissolut
44、ion of metallization and to soldering heat of surface mounting devices (SMD) IEC 60286-3, Packaging of components for automatic handling Part 3: Packaging of surface mount components on continuous tapes IEC 60286-4, Packaging of components for automatic handling Part 4: Stick magazines for electroni
45、c components encapsulated in packages of form E and G IEC 60286-5, Packaging of components for automatic handling Part 5: Matrix trays (only available in English) IEC 61760-1, Surface mounting technology Part 1: Standard method for the specification of surface mounting components (SMDs) (only availa
46、ble in English) 3 General information 3.1 General component description The two-sided J lead family is a small outline family identified by the dimensions of the body size in inches. For example, the SOJ/300 has a body size of 0,300 in or 7,63 mm, the SOJ/350 has a body size of 0,350 in or 8,88 mm,
47、the SOJ/400 has a body size of 0,400 in or 10,12 mm, and the SOJ/450 has a body size of 0,450 in or 11,38 mm. Package lead counts range from 14 to 28 pins. Pitch is uniformly for all sizes, i.e. 1,27 mm. The small-outline J (SOJ) package has leads on two sides, similar to a DIP. The lead configurati
48、on, like the letter J, extends out the side of the package and bends under the package forming a J bend. The point of contact of the lead to the land pattern is at the apex of the J bend and is the basis for the span of the land pattern. The (inner) end of the J is called the heel, and the outer sid
49、e of the J is called the toe. 61188-5-4 IEC:2007 7 The leads shall be coplanar within 0,1 mm. That is, when the component is placed on a flat surface, no lead may be more than 0,1 mm off the flat surface. The SOJ package takes advantage of chips having parallel address or data line layouts. For example, memory ICs are often used in multiples, and bus lines connect to t