1、 IEC 62386-101 Edition 2.0 2014-11 INTERNATIONAL STANDARD NORME INTERNATIONALE Digital addressable lighting interface Part 101: General requirements System components Interface dclairage adressable numrique Partie 101: Exigences gnrales Composants de systme IEC 62386-101:2014-11(en-fr) colour inside
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19、Si vous dsirez nous donner des commentaires sur cette publication ou si vous avez des questions contactez-nous: csciec.ch. IEC 62386-101 Edition 2.0 2014-11 INTERNATIONAL STANDARD NORME INTERNATIONALE Digital addressable lighting interface Part 101: General requirements System components Interface d
20、clairage adressable numrique Partie 101: Exigences gnrales Composants de systme INTERNATIONAL ELECTROTECHNICAL COMMISSION COMMISSION ELECTROTECHNIQUE INTERNATIONALE XC ICS 29.140, 29.140.50 PRICE CODE CODE PRIX ISBN 978-2-8322-1910-2 Registered trademark of the International Electrotechnical Commiss
21、ion Marque dpose de la Commission Electrotechnique Internationale Warning! Make sure that you obtained this publication from an authorized distributor. Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agr. colour inside 2 IEC 62386-101:2014 IEC 2014 CONTENT
22、S FOREWORD . 7 INTRODUCTION . 9 1 Scope 10 2 Normative references 10 3 Terms and definitions 10 4 General . 15 4.1 Purpose 15 4.2 Version number 15 4.3 System structure and architecture . 15 4.4 System information flow 16 4.5 Command types 16 4.6 Bus units . 17 Transmitters and receivers in bus unit
23、s 17 4.6.1Control gear 17 4.6.2Input device . 17 4.6.3Single master application controller . 17 4.6.4Multi-master application controller . 18 4.6.5Sharing an interface 18 4.6.6 4.7 Bus power supply and load calculations 19 Current demand coverage . 19 4.7.1Maximum signal current compliance 19 4.7.2S
24、implified system calculation . 19 4.7.3 4.8 Wiring . 19 Wiring structure . 19 4.8.1Wiring specification . 19 4.8.2 4.9 Insulation 20 4.10 Earthing of the bus 20 4.11 Power interruptions at bus units 20 Different levels of power interruptions 20 4.11.1Short power interruptions of external power suppl
25、y 20 4.11.2External power cycle . 21 4.11.3Short interruptions of bus power supply . 21 4.11.4Bus power down 21 4.11.5System start-up timing . 21 4.11.6 5 Electrical specification . 23 5.1 General . 23 5.2 Marking of the interface 23 5.3 Capacitors between the interface and earth 23 5.4 Signal volta
26、ge rating . 23 5.5 Signal current rating 24 5.6 Marking of bus powered bus unit . 24 5.7 Signal rise time and fall time . 24 6 Bus power supply 26 6.1 General . 26 6.2 Marking of the bus power supply terminals 26 6.3 Capacitors between the interface and earth 26 IEC 62386-101:2014 IEC 2014 3 6.4 Vol
27、tage rating . 26 6.5 Current rating 26 General current rating 26 6.5.1Single bus power supply current rating 27 6.5.2Integrated bus power supply current rating 27 6.5.3Dynamic behaviour of the bus power supply 27 6.5.4 6.6 Bus power supply timing requirements 28 Short power supply interruptions 28 6
28、.6.1Short circuit behaviour . 29 6.6.2 7 Transmission protocol structure . 29 7.1 General . 29 7.2 Bit encoding 29 Start bit and data bit encoding . 29 7.2.1Stop condition encoding 30 7.2.2 7.3 Frame description . 30 7.4 Frame types 30 16 bit forward frame . 30 7.4.124 bit forward frame . 30 7.4.2Re
29、served forward frame 30 7.4.3Backward frame . 30 7.4.4Proprietary forward frames 30 7.4.5 8 Timing . 31 8.1 Transmitter timing . 31 Transmitter bit timing . 31 8.1.1Transmitter frame sequence timing 32 8.1.2 8.2 Receiver timing . 32 Receiver bit timing . 32 8.2.1Receiver bit timing violation . 34 8.
30、2.2Receiver frame size violation . 34 8.2.3Receiver frame sequence timing 34 8.2.4Reception of backward frames . 35 8.2.5 8.3 Multi-master transmitter timing 35 Multi-master transmitter bit timing 35 8.3.1Multi-master transmitter frame sequence timing . 36 8.3.2 9 Method of operation . 36 9.1 Collis
31、ion avoidance, collision detection and collision recovery 36 General . 36 9.1.1Collision avoidance 37 9.1.2Collision detection . 37 9.1.3Collision recovery 38 9.1.4 9.2 Transactions . 39 9.3 Send-twice forward frames and send-twice commands . 40 9.4 Command iteration 40 9.5 Usage of a shared interfa
32、ce 41 General . 41 9.5.1Backward frames . 41 9.5.2Forward frames . 41 9.5.3 9.6 Use of multiple bus power supplies . 41 4 IEC 62386-101:2014 IEC 2014 9.7 Command execution . 42 10 Declaration of variables . 42 11 Definition of commands . 42 12 Test procedures 42 12.1 General notes on test 42 Abbrevi
33、ations . 42 12.1.1Ambient temperature . 42 12.1.2External power supply voltage and frequency 43 12.1.3Measurement requirements . 43 12.1.4Test signal generators and bus voltage sources 43 12.1.5Deviation from documentation . 43 12.1.6Test setup . 43 12.1.7Notation . 43 12.1.8 12.2 General interface
34、tests 49 Label and literature check 49 12.2.1Interface marking check . 49 12.2.2Bus powered bus unit marking check . 50 12.2.3Bus power supply marking check . 52 12.2.4Insulation test 54 12.2.5Capacitor check . 55 12.2.6 12.3 Bus power supply tests . 55 Voltage rating test . 55 12.3.1Voltage rise ti
35、me test . 56 12.3.2Current rating test 56 12.3.3Dynamic behaviour test . 58 12.3.4Power-on open circuit test . 60 12.3.5Power-on timing test 61 12.3.6Power supply short interruptions test . 62 12.3.7Power supply short circuit test . 63 12.3.8Power supply current consumption test 64 12.3.9 12.4 Contr
36、ol device tests 65 12.5 Control gear tests . 65 Annex A (informative) Background information for systems . 66 A.1 Wiring information . 66 A.2 System architectures 67 A.2.1 General . 67 A.2.2 Single master architecture . 67 A.2.3 Multi-master architecture with one application controller 68 A.2.4 Mult
37、i-master architecture with more than one application controller . 69 A.2.5 Multi-master architecture with integrated input device 70 A.2.6 Multi-master architecture with integrated input device and power supply 71 A.3 Collision detection 72 A.4 Timing definition explanations . 73 A.4.1 General . 73
38、A.4.2 Receiver timing 73 A.4.3 Transmitter timing 73 A.4.4 Grey areas 74 A.5 Maximum current consumption calculation explanation . 74 IEC 62386-101:2014 IEC 2014 5 A.5.1 Single bus power supply 74 A.5.2 Multiple bus power supplies . 75 A.5.3 Redundant bus power supplies 76 A.6 Communication layer ov
39、erview 77 A.6.1 General . 77 A.6.2 Physical layer 77 A.6.3 Data link layer . 77 A.6.4 Network layer 77 A.6.5 Transport layer 78 A.6.6 Session layer . 78 A.6.7 Presentation layer . 78 A.6.8 Application layer 78 Bibliography 79 Figure 1 IEC 62386 graphical overview 9 Figure 2 System structure example
40、16 Figure 3 Communication between bus units (example) . 16 Figure 4 Example of a shared interface 18 Figure 5 Start up timing example . 22 Figure 6 Maximum signal rise and fall time measurements . 25 Figure 7 Minimum signal rise and fall time measurements 25 Figure 8 Bus power supply current behavio
41、ur . 28 Figure 9 Bus power supply voltage behaviour 28 Figure 10 Frame example 29 Figure 11 Bi-phase encoded bits 30 Figure 12 Bit timing example 31 Figure 13 Settling time illustration 32 Figure 14 Receiver timing decision example 34 Figure 15 Collision detection timing decision example 38 Figure 1
42、6 Collision recovery example . 39 Figure 17 Current rating test signal 57 Figure 18 Dynamic behaviour test setup 58 Figure 19 Dynamic behaviour test signal 59 Figure A.1 Single master architecture example 68 Figure A.2 Multi-master architecture example with one application controller . 69 Figure A.3
43、 Multi-master architecture example with two application controllers 70 Figure A.4 Multi-master architecture example with integrated input device . 71 Figure A.5 Multi-master architecture example with integrate input device and bus power supply 72 Figure A.6 Collision detection timing diagram. 73 Fig
44、ure A.7 Transmitter and receiver timing illustration 74 Figure A.8 Bus power supply current values. 75 Figure A.9 Current demand coverage . 75 Figure A.10 Combination of 4 bus power supplies 76 Figure A.11 Redundant bus power supplies . 76 6 IEC 62386-101:2014 IEC 2014 Table 1 System components 15 T
45、able 2 Transmitters and receivers in bus units . 17 Table 3 Power-interruption timing of external power . 20 Table 4 Power-interruption timing of bus power 20 Table 5 Short power interruptions 21 Table 6 Start-up timing. 22 Table 7 System voltage levels 23 Table 8 Receiver voltage levels . 23 Table
46、9 Transmitter voltage levels . 24 Table 10 Current rating 24 Table 11 Signal rise and fall times . 25 Table 12 Bus power supply output voltage . 26 Table 13 Bus power supply current rating 27 Table 14 Bus power supply dynamic behaviour 27 Table 15 Short circuit timing behaviour 29 Table 16 Transmitt
47、er bit timing . 32 Table 17 Transmitter settling time values . 32 Table 18 Receiver timing starting at the beginning of a logical bit 33 Table 19 Receiver timing starting at an edge inside of a logical bit 33 Table 20 Receiver settling time values . 35 Table 21 Multi-master transmitter bit timing 35
48、 Table 22 Multi-master transmitter settling time values 36 Table 23 Checking a logical bit, starting at an edge at the beginning of the bit . 37 Table 24 Checking a logical bit, starting at an edge inside the bit 38 Table 25 Collision recovery timing . 39 Table 26 Transmitter command iteration timin
49、g 41 Table 27 Receiver command iteration timing 41 Table 28 Function call keywords 44 Table 29 Defined operators 47 Table A.1 Maximum cable length . 67 Table A.2 OSI layer model of IEC 62386 77 IEC 62386-101:2014 IEC 2014 7 INTERNATIONAL ELECTROTECHNICAL COMMISSION _ DIGITAL ADDRESSABLE LIGHTING INTERFACE Part
